1 /*-
50  * This is the top-level PLL clock on the IPQ4018/IPQ4019.
62 	uint32_t offset;  member
73 	uint64_t vco, parent_rate;  in qcom_clk_fepll_recalc()  local
79 		device_printf(clknode_get_device(sc->clknode),  in qcom_clk_fepll_recalc()
87 	CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode));  in qcom_clk_fepll_recalc()
88 	CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->offset, &reg);  in qcom_clk_fepll_recalc()
89 	CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode));  in qcom_clk_fepll_recalc()
91 	fdbkdiv = (reg >> sc->fdbkdiv_shift) &  in qcom_clk_fepll_recalc()
92 	    ((1U << sc->fdbkdiv_width) - 1);  in qcom_clk_fepll_recalc()
93 	refclkdiv = (reg >> sc->refclkdiv_shift) &  in qcom_clk_fepll_recalc()
94 	    ((1U << sc->refclkdiv_width) - 1);  in qcom_clk_fepll_recalc()
96 	vco = parent_rate / refclkdiv;  in qcom_clk_fepll_recalc()
97 	vco = vco * 2;  in qcom_clk_fepll_recalc()
98 	vco = vco * fdbkdiv;  in qcom_clk_fepll_recalc()
100 	*freq = vco;  in qcom_clk_fepll_recalc()
134 	clk = clknode_create(clkdom, &qcom_clk_fepll_class, &clkdef->clkdef);  in qcom_clk_fepll_register()
139 	sc->clknode = clk;  in qcom_clk_fepll_register()
141 	sc->offset = clkdef->offset;  in qcom_clk_fepll_register()
142 	sc->fdbkdiv_shift = clkdef->fdbkdiv_shift;  in qcom_clk_fepll_register()
143 	sc->fdbkdiv_width = clkdef->fdbkdiv_width;  in qcom_clk_fepll_register()
144 	sc->refclkdiv_shift = clkdef->refclkdiv_shift;  in qcom_clk_fepll_register()
145 	sc->refclkdiv_width = clkdef->refclkdiv_width;  in qcom_clk_fepll_register()