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/linux/drivers/clk/meson/
H A Dvclk.h15 * @enable: vclk enable field
16 * @reset: vclk reset field
34 * @enable: vclk divider enable field
35 * @reset: vclk divider reset field
/linux/drivers/gpu/drm/radeon/
H A Drs780_dpm.c570 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
587 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
727 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rs780_parse_pplib_non_clock_info()
730 rps->vclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
736 rps->vclk = RS780_DEFAULT_VCLK_FREQ; in rs780_parse_pplib_non_clock_info()
944 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
993 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
H A Dsumo_dpm.c822 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
838 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_before_set_eng_clock()
856 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_after_set_eng_clock()
1412 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in sumo_parse_pplib_non_clock_info()
1415 rps->vclk = 0; in sumo_parse_pplib_non_clock_info()
1803 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1826 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1834 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
H A Dtrinity_dpm.c850 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
862 if ((rps1->vclk == rps2->vclk) && in trinity_uvd_clocks_equal()
895 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
906 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1410 if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) && in trinity_get_uvd_clock_index()
1644 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in trinity_parse_pplib_non_clock_info()
1647 rps->vclk = 0; in trinity_parse_pplib_non_clock_info()
1886 pi->sys_info.uvd_clock_table_entries[i].vclk = in trinity_parse_sys_info_table()
1972 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
1997 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
H A Drv6xx_dpm.c1518 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_before_set_eng_clock()
1525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1535 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_after_set_eng_clock()
1542 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1803 rps->vclk = RV6XX_DEFAULT_VCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1806 rps->vclk = 0; in rv6xx_parse_pplib_non_clock_info()
2014 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2046 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
H A Drv770_dpm.c1440 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_before_set_eng_clock()
1447 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1457 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_after_set_eng_clock()
1464 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2155 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rv7xx_parse_pplib_non_clock_info()
2158 rps->vclk = 0; in rv7xx_parse_pplib_non_clock_info()
2163 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2164 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2441 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2485 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
/linux/drivers/video/fbdev/nvidia/
H A Dnv_hw.c380 static void nv4UpdateArbitrationSettings(unsigned VClk, in nv4UpdateArbitrationSettings() argument
402 sim_data.pclk_khz = VClk; in nv4UpdateArbitrationSettings()
618 static void nv10UpdateArbitrationSettings(unsigned VClk, in nv10UpdateArbitrationSettings() argument
642 sim_data.pclk_khz = VClk; in nv10UpdateArbitrationSettings()
676 static void nForceUpdateArbitrationSettings(unsigned VClk, in nForceUpdateArbitrationSettings() argument
744 sim_data.pclk_khz = VClk; in nForceUpdateArbitrationSettings()
771 unsigned VClk, Freq; in CalcVClock() local
776 VClk = (unsigned)clockIn; in CalcVClock()
787 Freq = VClk << P; in CalcVClock()
790 N = ((VClk << P) * M) / par->CrystalFreqKHz; in CalcVClock()
[all …]
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Darb.c193 nv04_update_arb(struct drm_device *dev, int VClk, int bpp, in nv04_update_arb() argument
205 sim_data.pclk_khz = VClk; in nv04_update_arb()
252 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) in nouveau_calc_arb() argument
258 nv04_update_arb(dev, vclk, bpp, burst, lwm); in nouveau_calc_arb()
/linux/drivers/video/fbdev/via/
H A Dvt1636.c186 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3324()
210 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3327()
227 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3364()
/linux/drivers/gpu/drm/renesas/rz-du/
H A Drzg2l_mipi_dsi.c83 struct clk *vclk; member
554 clk_set_rate(dsi->vclk, mode_freq * KILO); in rzg2l_dphy_conf_clks()
555 vclk_rate = clk_get_rate(dsi->vclk); in rzg2l_dphy_conf_clks()
557 dev_dbg(dsi->dev, "Requested vclk rate %lu, actual %lu mismatch\n", in rzg2l_dphy_conf_clks()
560 * Relationship between hsclk and vclk must follow in rzg2l_dphy_conf_clks()
561 * vclk * bpp = hsclk * 8 * lanes in rzg2l_dphy_conf_clks()
562 * where vclk: video clock (Hz) in rzg2l_dphy_conf_clks()
1169 * vclk * bpp = hsclk * 8 * num_lanes in rzg2l_mipi_dsi_host_attach()
1171 * vclk * DSI_AB_divider = hsclk * 16 in rzg2l_mipi_dsi_host_attach()
1421 dsi->vclk = devm_clk_get(dsi->dev, "vclk"); in rzg2l_mipi_dsi_probe()
[all …]
/linux/drivers/tty/serial/8250/
H A D8250_aspeed_vuart.c425 struct clk *vclk; in aspeed_vuart_probe() local
465 vclk = devm_clk_get_enabled(dev, NULL); in aspeed_vuart_probe()
466 if (IS_ERR(vclk)) { in aspeed_vuart_probe()
467 rc = dev_err_probe(dev, PTR_ERR(vclk), "clk or clock-frequency not defined\n"); in aspeed_vuart_probe()
471 port.port.uartclk = clk_get_rate(vclk); in aspeed_vuart_probe()
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu_v13_0_5_ppsmc.h52 #define PPSMC_MSG_SetSoftMaxVcn 17 ///< Set soft max for VCN clocks (VCLK and DCLK)
59 #define PPSMC_MSG_SetSoftMinVcn 24 ///< Set soft min for VCN clocks (VCLK and DCLK)
H A Dsmu_v13_0_1_ppsmc.h65 #define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN clocks (VCLK and DCL…
75 #define PPSMC_MSG_SetSoftMaxVcn 0x1F ///< Set soft max for VCN clocks (VCLK and DCL…
H A Dsmu_v13_0_4_ppsmc.h74 #define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN clocks (VCLK and DCL…
87 #define PPSMC_MSG_SetSoftMaxVcn 0x1F ///< Set soft max for VCN clocks (VCLK and DCL…
/linux/drivers/video/fbdev/aty/
H A Dmach64_ct.c73 * VCLK Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3
90 * - Generate the pixel clock for the LCD monitor (instead of VCLK)
216 printk(KERN_CRIT "atyfb: vclk out of range\n"); in aty_valid_pll_ct()
229 printk("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n", in aty_valid_pll_ct()
232 pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */ in aty_valid_pll_ct()
314 /* Reset VCLK generator */ in aty_set_pll_ct()
337 /* End VCLK generator reset */ in aty_set_pll_ct()
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpower_state.h144 uint32_t VCLK; member
184 unsigned long vclk; member
/linux/Documentation/devicetree/bindings/display/
H A Dxylon,logicvc-display.yaml45 # vclk is required and must be provided as first item.
46 - const: vclk
228 clock-names = "vclk", "lvdsclk";
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043u.dtsi139 clock-names = "aclk", "pclk", "vclk";
151 clock-names = "aclk", "pclk", "vclk";
163 clock-names = "aclk", "pclk", "vclk";
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h38 uint32_t vclk; member
120 uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu8_hwmgr.c140 if (clock <= ptable->entries[i].vclk) in smu8_get_uvd_level()
148 if (clock >= ptable->entries[i].vclk) in smu8_get_uvd_level()
512 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; in smu8_upload_pptable_to_smu()
599 clock = table->entries[level].vclk; in smu8_init_uvd_limit()
601 clock = table->entries[table->count - 1].vclk; in smu8_init_uvd_limit()
1437 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in smu8_dpm_get_pp_table_entry()
1752 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; in smu8_read_sensor() local
1786 vclk = uvd_table->entries[uvd_index].vclk; in smu8_read_sensor()
1787 *((uint32_t *)value) = vclk; in smu8_read_sensor()
1922 ptable->entries[ptable->count - 1].vclk; in smu8_dpm_update_uvd_dpm()
/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c18 * VCLK is the "Pixel Clock" frequency generator from a dedicated PLL.
34 * | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
39 * Final clocks can take input for either VCLK or VCLK2, but
40 * VCLK is the preferred path for HDMI clocking and VCLK2 is the
43 * VCLK and VCLK2 have fixed divided clocks paths for /1, /2, /4, /6 or /12.
788 /* Match 1000/1001 variant: vclk deviation has to be less than 1kHz in meson_vclk_freqs_are_matching_param()
905 /* Set VCLK div */ in meson_vclk_set()
1120 pr_err("Fatal Error, invalid HDMI vclk freq %lluHz\n", in meson_vclk_setup()
/linux/drivers/video/fbdev/sis/
H A Dinit.c2021 /* RESET VCLK */
2173 /* VCLK */
2268 SiS_DoCalcDelay(struct SiS_Private *SiS_Pr, unsigned short MCLK, unsigned short VCLK, in SiS_DoCalcDelay() argument
2272 unsigned int longtemp = VCLK * colordepth; in SiS_DoCalcDelay()
2288 SiS_CalcDelay(struct SiS_Private *SiS_Pr, unsigned short VCLK, in SiS_CalcDelay() argument
2293 temp2 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 0); in SiS_CalcDelay()
2294 temp1 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 1); in SiS_CalcDelay()
2306 unsigned short temp, index, VCLK, MCLK, colorth; in SiS_SetCRT1FIFO_300() local
2311 /* Get VCLK */ in SiS_SetCRT1FIFO_300()
2313 VCLK = SiS_Pr->CSRClock; in SiS_SetCRT1FIFO_300()
[all …]
/linux/drivers/media/platform/renesas/rzg2l-cru/
H A Drzg2l-csi2.c114 struct clk *vclk; member
459 clk_disable_unprepare(csi2->vclk); in rzg2l_csi2_mipi_link_enable()
464 return clk_prepare_enable(csi2->vclk); in rzg2l_csi2_mipi_link_enable()
934 csi2->vclk = devm_clk_get(dev, "video"); in rzg2l_csi2_probe()
935 if (IS_ERR(csi2->vclk)) in rzg2l_csi2_probe()
936 return dev_err_probe(dev, PTR_ERR(csi2->vclk), in rzg2l_csi2_probe()
938 csi2->vclk_rate = clk_get_rate(csi2->vclk); in rzg2l_csi2_probe()
/linux/drivers/gpu/drm/logicvc/
H A Dlogicvc_drm.c158 .clk = &logicvc->vclk, in logicvc_clocks_prepare()
159 .name = "vclk", in logicvc_clocks_prepare()
224 &logicvc->vclk, in logicvc_clocks_unprepare()
H A Dlogicvc_drm.h57 struct clk *vclk; member

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