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/linux/arch/x86/include/uapi/asm/
H A Ddebugreg.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
7 debug registers. Registers 0-3 contain the addresses we wish to trap on */
14 /* Define a few things for the status register. We can use this to determine
21 * This is also the DR6 architectural value following Power-up, Reset or INIT.
24 * Transactional Memory (RTM), the DR6 register has been modified:
29 * 2) RTM flag (bit 16) is no longer reserved to 1 if the CPU supports
30 * restricted transactional memory. #DB occurred inside an RTM region
33 * Apparently, DR6.BLD and DR6.RTM are active low bits.
47 #define DR_STEP (0x4000) /* single-step */
52 bits - each field corresponds to one of the four debug registers,
[all …]
/linux/net/mpls/
H A Daf_mpls.c1 // SPDX-License-Identifier: GPL-2.0-only
31 /* max memory we will use for mpls_route */
41 static int label_limit = (1 << 20) - 1;
82 platform_label = mpls_dereference(net, net->mpls.platform_label); in mpls_route_input_rcu()
90 if (index >= net->mpls.platform_labels) in mpls_output_possible()
93 platform_label = rcu_dereference(net->mpls.platform_label); in mpls_output_possible()
99 return dev && (dev->flag in __mpls_nh_via()
1794 struct rtmsg *rtm; rtm_to_route_config() local
1976 struct rtmsg *rtm; mpls_dump_route() local
2095 struct rtmsg *rtm; mpls_valid_fib_dump_req() local
2288 struct rtmsg *rtm; mpls_valid_getroute_req() local
2354 struct rtmsg *rtm, *r; mpls_getroute() local
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/linux/Documentation/devicetree/bindings/spi/
H A Dsocionext,synquacer-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/socionext,synquacer-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext SynQuacer HS-SPI Controller
10 - Masahisa Kojima <masahisa.kojima@linaro.org>
11 - Jassi Brar <jaswinder.singh@linaro.org>
14 - $ref: spi-controller.yaml#
18 const: socionext,synquacer-spi
26 - description: core clock
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/linux/net/mctp/
H A Droute.c1 // SPDX-License-Identifier: GPL-2.0
3 * Management Component Transport Protocol (MCTP) - routing
56 sk_for_each_rcu(sk, &net->mctp.binds[hash]) { in mctp_lookup_bind_details()
59 if (!allow_net_any && msk->bind_net == MCTP_NET_ANY) in mctp_lookup_bind_details()
62 if (msk->bind_net != MCTP_NET_ANY && msk->bind_net != cb->net) in mctp_lookup_bind_details()
65 if (msk->bind_type != type) in mctp_lookup_bind_details()
68 if (msk->bind_peer_set && in mctp_lookup_bind_details()
69 !mctp_address_matches(msk->bind_peer_addr, src)) in mctp_lookup_bind_details()
72 if (!mctp_address_matches(msk->bind_local_addr, dest)) in mctp_lookup_bind_details()
87 /* TODO: look up in skb->cb? */ in mctp_lookup_bind()
[all …]
/linux/drivers/net/fddi/skfp/h/
H A Dskfbi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
41 /* 0x0001 - 0x0003: reserved */
49 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
52 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
53 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
54 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
55 #define B0_ST2L 0x001c /* read lower 16-bit of status reg 2 */
59 #define B0_MDRU 0x0028 /* r/w upper 16-bit of mem. data reg */
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/linux/net/ipv4/
H A Dfib_semantics.c1 // SPDX-License-Identifier: GPL-2.0-or-later
60 for (nhsel = 0, nh = (fi)->fib_nh; \
66 for (nhsel = 0, nexthop_nh = (struct fib_nh *)((fi)->fib_nh); \
75 int nhsel; const struct fib_nh *nh = (fi)->fib_nh; \
80 struct fib_nh *nexthop_nh = (struct fib_nh *)((fi)->fib_nh); \
114 .error = -EINVAL,
118 .error = -EHOSTUNREACH,
122 .error = -EACCES,
126 .error = -EAGAIN,
130 .error = -EINVAL,
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H A Droute.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * ROUTE - implementation of the IP router.
34 * Alan Cox : Use __u32 properly
48 * Andi Kleen : Load-limit warning messages.
220 seq_printf(seq, "%-127s\n", in rt_cache_seq_show()
241 for (cpu = *pos-1; cpu < nr_cpu_ids; ++cpu) { in rt_cpu_seq_start()
283 0, /* st->in_hit */ in rt_cpu_seq_show()
284 st->in_slow_tot, in rt_cpu_seq_show()
285 st->in_slow_mc, in rt_cpu_seq_show()
286 st->in_no_route, in rt_cpu_seq_show()
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/linux/kernel/locking/
H A Drwsem.c1 // SPDX-License-Identifier: GPL-2.0
5 * Derived from asm-i386/semaphore.h
7 * Writer lock-stealing by Alex Shi <alex.shi@intel.com>
13 * Rwsem count bit fields re-definition and rwsem rearchitecture by
39 * - Bit 0: RWSEM_READER_OWNED - rwsem may be owned by readers (just a hint)
40 * - Bit 1: RWSEM_NONSPINNABLE - Cannot spin on a reader-owned lock
42 * When the rwsem is reader-owned and a spinning writer has timed out,
51 * for a free or reader-owned rwsem, the owner value may contain
61 * - rwsem is not currently writer owned
62 * - the handoff isn't set.
[all …]
/linux/include/linux/
H A Dmroute_base.h5 #include <linux/rhashtable-types.h>
13 * struct vif_device - interface representor for multicast routing
66 .vif_flags = vif->flags, in mr_call_vif_notifier()
87 .vif_flags = vif->flags, in mr_call_vif_notifiers()
104 #define VIF_EXISTS(_mrt, _idx) (!!rcu_access_pointer((_mrt)->vif_table[_idx].dev))
107 * MFC_STATIC - the entry was added statically (not by a routing daemon)
108 * MFC_OFFLOAD - the entry was offloaded to the hardware
116 * struct mr_mfc - common multicast routing entries
128 * @lastuse: time of last use of the group (traffic or update)
164 if (refcount_dec_and_test(&c->mfc_un.res.refcount)) in mr_cache_put()
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/linux/lib/zstd/common/
H A Dcpu.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
6 * This source code is licensed under both the BSD-style license (found in the
9 * You may select, at your option, one of the above-listed licenses.
37 * reserves ebx for use of its pic register so we must specially in ZSTD_cpuid()
170 B(rtm, 11)
/linux/Documentation/admin-guide/hw-vuln/
H A Dtsx_async_abort.rst1 .. SPDX-License-Identifier: GPL-2.0
3 TAA - TSX Asynchronous Abort
11 -------------------
23 ------------
28 CVE-2019-11135 TAA TSX Asynchronous Abort (TAA) condition on some
36 -------
43 hardware transactional memory support to improve performance of multi-threaded
58 Because the buffers are potentially shared between Hyper-Threads cross
59 Hyper-Thread attacks are possible.
61 The victim of a malicious actor does not need to make use of TSX. Only the
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/linux/arch/x86/kvm/
H A Dcpuid.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
55 cpuid_count(0xD, i, &xs->eax, &xs->ebx, &xs->ecx, &ign); in kvm_init_xstate_sizes()
74 offset = (xs->ecx & 0x2) ? ALIGN(ret, 64) : ret; in xstate_required_size()
76 offset = xs->ebx; in xstate_required_size()
77 ret = max(ret, offset + xs->eax); in xstate_required_size()
91 * KVM has a semi-arbitrary rule that querying the guest's CPUID model in kvm_find_cpuid_entry2()
95 * path, e.g. the core VM-Enter/VM-Exit run loop. Nothing will break in kvm_find_cpuid_entry2()
105 if (e->function != function) in kvm_find_cpuid_entry2()
109 * If the index isn't significant, use the first entry with a in kvm_find_cpuid_entry2()
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H A Dpmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine -- Performance Monitoring Unit support
46 /* Instruction-Accurate PDIR (PDIR++) */
58 * - Each perf counter is defined as "struct kvm_pmc";
59 * - There are two types of perf counters: general purpose (gp) and fixed.
63 * - pmu.c understands the difference between gp counters and fixed counters.
64 * However AMD doesn't support fixed-counters;
65 * - There are three types of index to access perf counters (PMC):
68 * MSR_F15H_PERF_CTRn, where MSR_F15H_PERF_CTR[0-3] are
79 * * Intel: [0 .. KVM_MAX_NR_INTEL_GP_COUNTERS-1] <=> gp counters
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H A Dx86.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
16 * Ben-Ami Yassour <benami@il.ibm.com>
48 #include <linux/user-return-notifier.h>
107 ((struct kvm_vcpu *)(ctxt)->vcpu)
110 * - enable syscall per default because its emulated by KVM
111 * - enable LME and LMA per default on 64 bit KVM
145 *(((struct kvm_x86_ops *)0)->func));
148 #include <asm/kvm-x86-ops.h>
162 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
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/linux/arch/x86/include/asm/
H A Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define NCAPINTS 22 /* N 32-bit words worth of info */
9 #define NBUGINTS 2 /* N 32-bit bug flags */
17 * please update the table in kernel/cpu/cpuid-deps.c as well.
20 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
26 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
37 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */
47 #define X86_FEATURE_HT ( 0*32+28) /* "ht" Hyper-Threading */
49 #define X86_FEATURE_IA64 ( 0*32+30) /* "ia64" IA-64 processor */
52 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
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/linux/tools/arch/x86/include/asm/
H A Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define NCAPINTS 22 /* N 32-bit words worth of info */
9 #define NBUGINTS 2 /* N 32-bit bug flags */
17 * please update the table in kernel/cpu/cpuid-deps.c as well.
20 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
26 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
37 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */
47 #define X86_FEATURE_HT ( 0*32+28) /* "ht" Hyper-Threading */
49 #define X86_FEATURE_IA64 ( 0*32+30) /* "ia64" IA-64 processor */
52 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
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H A Dmsr-index.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* x86-64 specific MSRs */
23 #define _EFER_LMA 10 /* Long mode active (read-only) */
130 #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */
179 * Indicates RET may use predictors
194 * Not susceptible to Post-Barrier
233 #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
294 #define LBR_INFO_BR_CNTR_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_BITS - 1, 0)
295 #define LBR_INFO_BR_CNTR_FULL_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_NUM * LBR_INFO_BR_CNTR_BITS - 1, 0)
416 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
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/linux/tools/perf/pmu-events/arch/x86/haswell/
H A Dpipeline.json20 "BriefDescription": "Speculative and retired macro-conditional branches.",
28 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
60 "BriefDescription": "Not taken macro-conditional branches.",
68 "BriefDescription": "Taken speculative and retired macro-conditional branches.",
76 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
228 …"PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Cou…
498 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
503 … "BriefDescription": "Number of instructions retired. General Counter - architectural event",
523 … have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exc…
527 …-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For …
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/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Dpipeline.json20 "BriefDescription": "Speculative and retired macro-conditional branches.",
28 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
60 "BriefDescription": "Not taken macro-conditional branches.",
68 "BriefDescription": "Taken speculative and retired macro-conditional branches.",
76 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
228 …"PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Cou…
498 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
503 … "BriefDescription": "Number of instructions retired. General Counter - architectural event",
523 … have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exc…
527 …-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For …
[all …]
/linux/arch/x86/events/intel/
H A Dds.c1 // SPDX-License-Identifier: GPL-2.0
215 OP_LH | LEVEL(MSC) | P(SNOOP, NONE), /* 0x10: Memory-side Cache Hit */
275 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) in precise_datala_hsw()
277 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW) in precise_datala_hsw()
288 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) { in precise_datala_hsw()
314 /* Retrieve the latency data for e-core of ADL */
321 hybrid_pmu(event->pmu)->pmu_type == hybrid_big); in __grt_latency_data()
324 val = hybrid_var(event->pmu, pebs_data_source)[dse]; in __grt_latency_data()
347 /* Retrieve the latency data for e-core of MTL */
368 val = hybrid_var(event->pmu, pebs_data_source)[status & PERF_PEBS_DATA_SOURCE_MASK]; in lnc_latency_data()
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/linux/net/ipv6/
H A Dip6_fib.c1 // SPDX-License-Identifier: GPL-2.0-or-later
76 list_for_each_entry(w, &(net)->ipv6.fib6_walkers, lh)
80 write_lock_bh(&net->ipv6.fib6_walker_lock); in fib6_walker_link()
81 list_add(&w->lh, &net->ipv6.fib6_walkers); in fib6_walker_link()
82 write_unlock_bh(&net->ipv in fib6_walker_link()
650 struct rtmsg *rtm = nlmsg_data(nlh); inet6_dump_fib() local
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/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv1 # SPDX-License-Identifier: CC0-1.0
2 # Generator: x86-cpuid-db v2.4
5 # Auto-generated file.
6 # Please submit all updates and bugfixes to https://x86-cpuid.org
16 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3
17 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11
18 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 -
[all...]
/linux/drivers/net/fddi/skfp/
H A Dfplustm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
49 #define DUMMY_READ() smc->hw.mc_dummy = (u_short) inp(ADDR(B0_RAP))
52 while ((inpw(FM_A(FM_STMCHN)) & FM_SNPPND) && k) k--;\
59 while (!(inpw(FM_A(FM_AFSTAT)) & FM_DONE) && k) k--;\
76 #define MA smc->hw.fddi_canon_addr
78 #define MA smc->hw.fddi_home_addr
114 smc->mib.m[MAC0].fddiMACFrame_Ct = in mac_update_counter()
115 (smc->mib.m[MAC0].fddiMACFrame_Ct & 0xffff0000L) in mac_update_counter()
117 smc->mib.m[MAC0].fddiMACLost_Ct = in mac_update_counter()
118 (smc->mib.m[MAC0].fddiMACLost_Ct & 0xffff0000L) in mac_update_counter()
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/linux/Documentation/virt/kvm/
H A Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
24 - System ioctls: These query and set global attributes which affect the
28 - VM ioctls: These query and set attributes that affect an entire virtual
35 - vcpu ioctls: These query and set attributes that control the operation
43 - device ioctls: These query and set attributes that control the operation
92 facility that allows backward-compatible extensions to the API to be
98 set of ioctls is available for application use.
133 -----------------------
150 -----------------
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/linux/tools/perf/util/
H A Dintel-pt.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2013-2015, Intel Corporation.
28 #include "thread-stack.h"
35 #include "intel-pt.h"
38 #include "util/synthetic-events.h"
39 #include "time-utils.h"
43 #include "intel-pt-decoder/intel-pt-log.h"
44 #include "intel-pt-decoder/intel-pt-decoder.h"
45 #include "intel-pt-decoder/intel-pt-insn-decoder.h"
46 #include "intel-pt-decoder/intel-pt-pkt-decoder.h"
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