Lines Matching +full:use +full:- +full:rtm
1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
16 #define NCAPINTS 22 /* N 32-bit words worth of info */
17 #define NBUGINTS 2 /* N 32-bit bug flags */
25 * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */
55 #define X86_FEATURE_HT ( 0*32+28) /* "ht" Hyper-Threading */
57 #define X86_FEATURE_IA64 ( 0*32+30) /* "ia64" IA-64 processor */
60 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
69 #define X86_FEATURE_LM ( 1*32+29) /* "lm" Long Mode (x86-64, 64-bit support) */
73 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
78 /* Other features, Linux-defined mapping, word 3 */
92 #define X86_FEATURE_PEBS ( 3*32+12) /* "pebs" Precise-Event Based Sampling */
101 #define X86_FEATURE_ALWAYS ( 3*32+21) /* Always-present feature */
107 #define X86_FEATURE_AMD_DCM ( 3*32+27) /* "amd_dcm" AMD multi-node processor */
108 #define X86_FEATURE_APERFMPERF ( 3*32+28) /* "aperfmperf" P-State hardware coordination feedback c…
113 /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */
114 #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
116 #define X86_FEATURE_DTES64 ( 4*32+ 2) /* "dtes64" 64-bit Debug Store */
118 #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */
123 #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* "ssse3" Supplemental SSE-3 */
126 #define X86_FEATURE_FMA ( 4*32+12) /* "fma" Fused multiply-add */
132 #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */
133 #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */
142 #define X86_FEATURE_F16C ( 4*32+29) /* "f16c" 16-bit FP conversions */
146 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
149 #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
150 #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
163 #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* "cr8_legacy" CR8 in 32-bit mode */
165 #define X86_FEATURE_SSE4A ( 6*32+ 6) /* "sse4a" SSE-4A */
182 #define X86_FEATURE_PTSC ( 6*32+27) /* "ptsc" Performance time-stamp counter */
187 * Auxiliary flags: Linux defined - For features scattered in various
200 #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* "hw_pstate" AMD HW-PState */
202 #define X86_FEATURE_XCOMPACTED ( 7*32+10) /* Use compacted XSTATE (XSAVES or XSAVEC) */
205 #define X86_FEATURE_RSB_VMEXIT ( 7*32+13) /* Fill RSB on VM-Exit */
214 #define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* Use IBRS during runtime firmware calls */
233 #define X86_FEATURE_EPT_AD ( 8*32+17) /* "ept_ad" Intel Extended Page Table access-dirty bit */
240 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
252 #define X86_FEATURE_RTM ( 9*32+11) /* "rtm" Restricted Transactional Memory */
257 #define X86_FEATURE_AVX512F ( 9*32+16) /* "avx512f" AVX-512 Foundation */
258 #define X86_FEATURE_AVX512DQ ( 9*32+17) /* "avx512dq" AVX-512 DQ (Double/Quad granular) Instructio…
262 #define X86_FEATURE_AVX512IFMA ( 9*32+21) /* "avx512ifma" AVX-512 Integer Fused Multiply-Add instr…
266 #define X86_FEATURE_AVX512PF ( 9*32+26) /* "avx512pf" AVX-512 Prefetch */
267 #define X86_FEATURE_AVX512ER ( 9*32+27) /* "avx512er" AVX-512 Exponential and Reciprocal */
268 #define X86_FEATURE_AVX512CD ( 9*32+28) /* "avx512cd" AVX-512 Conflict Detection */
270 #define X86_FEATURE_AVX512BW ( 9*32+30) /* "avx512bw" AVX-512 BW (Byte/Word granular) Instructions…
271 #define X86_FEATURE_AVX512VL ( 9*32+31) /* "avx512vl" AVX-512 VL (128/256 Vector Length) Extension…
281 * Extended auxiliary flags: Linux defined - for features scattered in various
293 #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* Per-thread Memory Bandwidth Allocation */
299 #define X86_FEATURE_RETPOLINE_LFENCE (11*32+13) /* Use LFENCE for Spectre variant 2 */
300 #define X86_FEATURE_RETHUNK (11*32+14) /* Use REturn THUNK */
302 #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* Use IBPB during runtime firmware calls */
319 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
324 #define X86_FEATURE_FZRM (12*32+10) /* Fast zero-length REP MOVSB */
329 #define X86_FEATURE_WRMSRNS (12*32+19) /* Non-serializing WRMSR */
334 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
343 …E_AMD_STIBP_ALWAYS_ON (13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */
359 #define X86_FEATURE_HWP (14*32+ 7) /* "hwp" Intel Hardware P-states */
374 #define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* "flushbyasid" Flush-by-ASID support */
386 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
396 #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* "vpclmulqdq" Carry-Less Multiplication Double Quadwor…
398 …512_BITALG (16*32+12) /* "avx512_bitalg" Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */
401 #define X86_FEATURE_LA57 (16*32+16) /* "la57" 5-level page tables */
410 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
415 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
416 #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* "avx512_4vnniw" AVX-512 Neural Network Instructions…
417 #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* "avx512_4fmaps" AVX-512 Multiply Accumulation Singl…
419 #define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* "avx512_vp2intersect" AVX-512 Intersect for D…
422 #define X86_FEATURE_RTM_ALWAYS_ABORT (18*32+11) /* RTM transaction always aborts */
441 /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
445 #define X86_FEATURE_SEV_ES (19*32+ 3) /* "sev_es" AMD Secure Encrypted Virtualization - Encrypted …
446 #define X86_FEATURE_SEV_SNP (19*32+ 4) /* "sev_snp" AMD Secure Encrypted Virtualization - Secure N…
448 #define X86_FEATURE_SME_COHERENT (19*32+10) /* AMD hardware-enforced cache coherency */
449 #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" AMD SEV-ES full debug state swap support…
452 /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
454 #define X86_FEATURE_WRMSR_XX_BASE_NS (20*32+ 1) /* WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializi…
465 * Extended auxiliary flags: Linux defined - for features scattered in various
493 * 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional
496 #define X86_BUG_ESPFIX X86_BUG(9) /* IRET to 16-bit SS corrupts ESP/RSP high bits */
517 #define X86_BUG_SMT_RSB X86_BUG(29) /* "smt_rsb" CPU is vulnerable to Cross-Thread Return Address…
519 #define X86_BUG_TDX_PW_MCE X86_BUG(31) /* "tdx_pw_mce" CPU may incur #MC if non-TD software does p…