Lines Matching +full:use +full:- +full:rtm
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
41 /* 0x0001 - 0x0003: reserved */
49 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
52 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
53 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
54 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
55 #define B0_ST2L 0x001c /* read lower 16-bit of status reg 2 */
59 #define B0_MDRU 0x0028 /* r/w upper 16-bit of mem. data reg */
60 #define B0_MDRL 0x002c /* r/w lower 16-bit of mem. data reg */
63 #define B0_ST3U 0x0034 /* read upper 16-bit of status reg 3 */
64 #define B0_ST3L 0x0038 /* read lower 16-bit of status reg 3 */
65 #define B0_IMSK3U 0x003c /* r/w upper 16-bit of IMSK reg 3 */
66 #define B0_IMSK3L 0x0040 /* r/w lower 16-bit of IMSK reg 3 */
88 * - completely empty (this is the RAP Block window)
106 /* 0x010a - 0x010b: reserved */
107 /* Eprom registers are currently of no use */
112 #define B2_FAR 0x0110 /* 32 bit Flash-Prom Address Register/Counter */
113 #define B2_FDP 0x0114 /* 8 bit Flash-Prom Data Port */
114 /* 0x0115 - 0x0117: reserved */
117 /* 0x011a - 0x011f: reserved */
122 /* 0x012a - 0x012f: reserved */
127 /* 0x013a - 0x013f: reserved */
128 #define B2_RTM_INI 0x0140 /* 32 bit RTM init value */
129 #define B2_RTM_VAL 0x0144 /* 32 bit RTM value */
130 #define B2_RTM_CRTL 0x0148 /* 8 bit RTM control */
131 #define B2_RTM_TEST 0x0149 /* 8 Bit RTM Test */
146 /* 0x016a - 0x017f: reserved */
174 /* 0x0238 - 0x023f: reserved */
189 /* 0x0270 - 0x027c: reserved */
209 /* 0x02b8 - 0x02bc: reserved */
225 /* 0x02f8 - 0x02fc: reserved */
230 /* External PLC-S registers (SN2 compatibility for DV) */
237 /* DAS PLC-S Registers */
240 * Bank 8 - 15
244 /*---------------------------------------------------------------------------*/
385 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
405 /* The EPROM register are currently of no use */
411 /* B2_FAR 32 bit Flash-Prom Address Register/Counter */
414 /* B2_FDP 8 bit Flash-Prom Data Port */
433 /* B2_RTM_INI 32 bit RTM init value */
434 /* B2_RTM_VAL 32 bit RTM value */
435 /* B2_RTM_CRTL 8 bit RTM control */
436 /* B2_RTM_TEST 8 Bit RTM Test */
442 #define GET_TOK_CT (1<<4) /* Bit 4: Get the Token Counter (RTM) */
443 #define TIM_RES_TOK (1<<3) /* Bit 3: RTM Status: 1 == restricted */
445 #define TIM_START (1<<2) /* Bit 2: Start Timer (TI,WDOG,RTM,IRQ_MOD)*/
446 #define TIM_STOP (1<<1) /* Bit 1: Stop Timer (TI,WDOG,RTM,IRQ_MOD) */
447 #define TIM_CL_IRQ (1<<0) /* Bit 0: Clear Timer IRQ (TI,WDOG,RTM) */
449 #define TIM_T_ON (1<<2) /* Bit 2: Test mode on (TI,WDOG,RTM,IRQ_MOD) */
450 #define TIM_T_OFF (1<<1) /* Bit 1: Test mode off (TI,WDOG,RTM,IRQ_MOD) */
451 #define TIM_T_STEP (1<<0) /* Bit 0: Test step (TI,WDOG,RTM,IRQ_MOD) */
694 * physical address offset + IO-Port base address
697 #define ADDR(a) (char far *) smc->hw.iop+(a)
698 #define ADDRS(smc,a) (char far *) (smc)->hw.iop+(a)
700 #define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \
701 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
702 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
703 #define ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \
704 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
705 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
759 #define STI_FBI() outpd(ADDR(B0_IMSK),smc->hw.is_imask)
761 #define STI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask)
765 #define STI_FBI_SMP(smc,iop) outpd((iop)+B0_IMSK,(smc)->hw.is_imask)
768 /*--------------------------------------------------------------------------*/
811 * With SuperNet 3 PHY-A and PHY S are identical.
832 /* read FORMAC+ 32-bit status register */
842 /* read FORMAC+ 32-bit status register */