/linux/Documentation/devicetree/bindings/usb/ |
H A D | nvidia,tegra124-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces 20 - description: NVIDIA Tegra124 21 const: nvidia,tegra124-xusb 23 - description: NVIDIA Tegra132 [all …]
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H A D | nvidia,tegra210-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces 18 const: nvidia,tegra210-xusb 22 - description: base and length of the xHCI host registers 23 - description: base and length of the XUSB FPCI registers [all …]
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H A D | mediatek,mtk-xhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: MediaTek USB3 xHCI 11 - Chunfeng Yun <chunfeng.yun@mediatek.com> 14 - $ref: usb-xhci.yaml 19 case 2: supports dual-role mode, and the host is based on xHCI driver. 25 - enum: 26 - mediatek,mt2701-xhci [all …]
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H A D | nvidia,tegra194-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces 18 const: nvidia,tegra194-xusb 22 - description: base and length of the xHCI host registers 23 - description: base and length of the XUSB FPCI registers [all …]
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H A D | nvidia,tegra186-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra186-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces 18 const: nvidia,tegra186-xusb 22 - description: base and length of the xHCI host registers 23 - description: base and length of the XUSB FPCI registers [all …]
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H A D | mediatek,mtu3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: MediaTek USB3 DRD Controller 11 - Chunfeng Yun <chunfeng.yun@mediatek.com> 14 - $ref: usb-drd.yaml 23 - enum: 24 - mediatek,mt2712-mtu3 25 - mediatek,mt8173-mtu3 26 - mediatek,mt8183-mtu3 [all …]
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H A D | nvidia,tegra-xudc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 14 - Nagarjuna Kristam <nkristam@nvidia.com> 15 - JC Kuo <jckuo@nvidia.com> 16 - Thierry Reding <treding@nvidia.com> 21 - enum: 22 - nvidia,tegra210-xudc # For Tegra210 23 - nvidia,tegra186-xudc # For Tegra186 [all …]
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H A D | renesas,usb3-peri.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/usb/renesas,usb3-peri.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 15 - items: 16 - enum: 17 - renesas,r8a774a1-usb3-peri # RZ/G2M 18 - renesas,r8a774b1-usb3-peri # RZ/G2N 19 - renesas,r8a774c0-usb3-peri # RZ/G2E [all …]
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H A D | rockchip,rk3399-dwc3.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Heiko Stuebner <heiko@sntech.de> 14 const: rockchip,rk3399-dwc3 16 '#address-cells': 19 '#size-cells': 26 - description: 28 - description: [all …]
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H A D | dwc3-xilinx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Mubin Sayyed <mubin.sayyed@amd.com> 11 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> 16 - enum: 17 - xlnx,zynqmp-dwc3 18 - xlnx,versal-dwc3 22 "#address-cells": [all …]
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H A D | realtek,rtd-dwc3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/usb/realtek,rtd-dwc3.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Stanley Chang <stanley_chang@realtek.com> 15 and USB 3.0 in host or dual-role mode. 20 - enum: 21 - realtek,rtd1295-dwc3 22 - realtek,rtd1315e-dwc3 23 - realtek,rtd1319-dwc3 [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | qcom,usb-ss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/qcom,usb-ss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org> 18 - qcom,usb-ss-28nm-phy 23 "#phy-cells": 28 - description: rpmcc clock 29 - description: PHY AHB clock 30 - description: SuperSpeed pipe clock [all …]
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/linux/drivers/usb/cdns3/ |
H A D | Kconfig | 8 dual-role controller. 9 It supports: dual-role switch, Host-only, and Peripheral-only. 17 tristate "Cadence USB3 Dual-Role Controller" 20 Say Y here if your system has a Cadence USB3 dual-role controller. 21 It supports: dual-role switch, Host-only, and Peripheral-only. 30 bool "Cadence USB3 device controller" 34 Cadence USBSS-DEV driver. 36 This controller supports FF, HS and SS mode. It doesn't support 40 bool "Cadence USB3 host controller" 51 tristate "Cadence USB3 support on PCIe-based platforms" [all …]
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H A D | cdns3-gadget.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 5 * Copyright (C) 2018-2019 Cadence. 6 * Copyright (C) 2017-2018 NXP 15 #include <linux/dma-direction.h> 18 * USBSS-DEV register interface. 23 * struct cdns3_usb_regs - device controller registers. 53 * @buf_addr: Address for On-chip Buffer operations. 54 * @buf_data: Data for On-chip Buffer operations. 55 * @buf_ctrl: On-chip Buffer Access Control. 123 /* USB_CONF - bitmasks */ [all …]
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/linux/drivers/phy/socionext/ |
H A D | phy-uniphier-usb3ss.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * phy-uniphier-usb3ss.c - SS-PHY driver for Socionext UniPhier USB3 controller 4 * Copyright 2015-2018 Socionext Inc. 73 writel(data, priv->base + SSPHY_TESTI); in uniphier_u3ssphy_testio_write() 74 readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_testio_write() 75 readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_testio_write() 82 u8 field_mask = GENMASK(p->field.msb, p->field.lsb); in uniphier_u3ssphy_set_param() 87 val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no); in uniphier_u3ssphy_set_param() 89 val = readl(priv->base + SSPHY_TESTO) & TESTO_DAT_MASK; in uniphier_u3ssphy_set_param() 93 data = field_mask & (p->value << p->field.lsb); in uniphier_u3ssphy_set_param() [all …]
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/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra124-nyan.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/input/input.h> 3 #include <dt-bindings/thermal/thermal.h> 14 stdout-path = "serial0:115200n8"; 20 * missing a unit-address. However, the bootloader on these Chromebook 22 * Adding the unit-address causes the bootloader to create a /memory 34 /delete-node/ memory@80000000; 40 vdd-supply = <&vdd_3v3_hdmi>; 41 pll-supply = <&vdd_hdmi_pll>; 42 hdmi-supply = <&vdd_5v0_hdmi>; [all …]
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H A D | tegra124-venice2.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 18 stdout-path = "serial0:115200n8"; 29 vdd-supply = <&vdd_3v3_hdmi>; 30 pll-supply = <&vdd_hdmi_pll>; 31 hdmi-supply = <&vdd_5v0_hdmi>; 33 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 34 nvidia,hpd-gpio = 41 avdd-io-hdmi-dp-supply = <&vdd_1v05_run>; [all …]
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/linux/Documentation/devicetree/bindings/connector/ |
H A D | usb-connector.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/connector/usb-connector.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rob Herring <robh@kernel.org> 20 - enum: 21 - usb-a-connector 22 - usb-b-connector 23 - usb-c-connector 25 - items: [all …]
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/linux/drivers/phy/qualcomm/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. 69 with USB3 and DisplayPort controllers on Qualcomm chips. 103 with USB3 controllers on Qualcomm chips. 111 PHY transceivers working only in USB3 mode on Qualcomm chips. This 124 controllers on Qualcomm chips. This driver supports the high-speed 133 Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm 142 Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm 160 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in 163 Support for the USB high-speed ULPI compliant phy on Qualcomm [all …]
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/linux/drivers/usb/host/ |
H A D | xhci-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. 11 #include <linux/dma-mapping.h> 236 } usb2, ulpi, hsic, usb3; member 321 return readl(tegra->fpci_base + offset); in fpci_readl() 327 writel(value, tegra->fpci_base + offset); in fpci_writel() 332 return readl(tegra->ipfs_base + offset); in ipfs_readl() 338 writel(value, tegra->ipfs_base + offset); in ipfs_writel() 343 return readl(tegra->bar2_base + offset); in bar2_readl() 349 writel(value, tegra->bar2_base + offset); in bar2_writel() [all …]
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/linux/drivers/phy/tegra/ |
H A D | xusb-tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. 27 ((x) ? (11 + ((x) - 1) * 6) : 0) 451 for (map = tegra210_usb3_map; map->type; map++) { in tegra210_usb3_lane_map() 452 if (map->index == lane->index && in tegra210_usb3_lane_map() 453 strcmp(map->type, lane->pad->soc->name) == 0) { in tegra210_usb3_lane_map() 454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n", in tegra210_usb3_lane_map() 455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map() 456 return map->port; in tegra210_usb3_lane_map() 460 return -EINVAL; in tegra210_usb3_lane_map() [all …]
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/linux/drivers/usb/mtu3/ |
H A D | mtu3.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * mtu3.h - MediaTek USB3 DRD header 35 #define MU3D_EP_TXCR0(epnum) (U3D_TX1CSR0 + (((epnum) - 1) * 0x10)) 36 #define MU3D_EP_TXCR1(epnum) (U3D_TX1CSR1 + (((epnum) - 1) * 0x10)) 37 #define MU3D_EP_TXCR2(epnum) (U3D_TX1CSR2 + (((epnum) - 1) * 0x10)) 39 #define MU3D_EP_RXCR0(epnum) (U3D_RX1CSR0 + (((epnum) - 1) * 0x10)) 40 #define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10)) 41 #define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10)) 43 #define USB_QMU_TQHIAR(epnum) (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4)) 44 #define USB_QMU_RQHIAR(epnum) (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4)) [all …]
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/linux/drivers/phy/amlogic/ |
H A D | phy-meson-g12a-usb3-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Amlogic G12A USB3 + PCIE Combo PHY driver 19 #include <dt-bindings/phy/phy.h> 79 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr() 80 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr() 82 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR); in phy_g12a_usb3_pcie_cr_bus_addr() 84 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, in phy_g12a_usb3_pcie_cr_bus_addr() 90 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr() 92 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, in phy_g12a_usb3_pcie_cr_bus_addr() 112 regmap_write(priv->regmap, PHY_R4, 0); in phy_g12a_usb3_pcie_cr_bus_read() [all …]
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