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/linux/drivers/usb/host/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # USB Host Controller Drivers
5 comment "USB Host Controller Drivers"
11 The Cypress C67x00 (EZ-Host/EZ-OTG) chips are dual-role
12 host/peripheral/OTG USB controllers.
21 tristate "xHCI HCD (USB 3.0) support"
24 The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
28 module will be called xhci-hcd.
90 tristate "xHCI support for Renesas R-Car SoCs"
96 found in Renesas R-Car ARM SoCs.
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H A Dehci-pci.c1 // SPDX-License-Identifier: GPL-2.0+
3 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
5 * Copyright (c) 2000-2004 by David Brownell
11 #include <linux/usb.h>
12 #include <linux/usb/hcd.h>
14 #include "ehci.h"
15 #include "pci-quirks.h"
17 #define DRIVER_DESC "EHCI PCI platform driver"
19 static const char hcd_name[] = "ehci-pci";
27 /*-------------------------------------------------------------------------*/
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H A Dehci-hub.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2001-2004 by David Brownell
6 /* this file is part of ehci-hcd.c */
8 /*-------------------------------------------------------------------------*/
11 * EHCI Root Hub ... the nonsharable stuff
16 /*-------------------------------------------------------------------------*/
22 static void unlink_empty_async_suspended(struct ehci_hcd *ehci);
26 return !udev->maxchild && udev->persist_enabled && in persist_enabled_on_companion()
27 udev->bus->root_hub->speed < USB_SPEED_HIGH; in persist_enabled_on_companion()
33 static void ehci_handover_companion_ports(struct ehci_hcd *ehci) in ehci_handover_companion_ports() argument
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/linux/Documentation/usb/
H A Dehci.rst2 EHCI driver
5 27-Dec-2002
7 The EHCI driver is used to talk to high speed USB 2.0 devices using
8 USB 2.0-capable host controller hardware. The USB 2.0 standard is
9 compatible with the USB 1.1 standard. It defines three transfer speeds:
11 - "High Speed" 480 Mbit/sec (60 MByte/sec)
12 - "Full Speed" 12 Mbit/sec (1.5 MByte/sec)
13 - "Low Speed" 1.5 Mbit/sec
15 USB 1.1 only addressed full speed and low speed. High speed devices
16 can be used on USB 1.1 systems, but they slow down to USB 1.1 speeds.
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/linux/Documentation/arch/x86/
H A Dearlyprintk.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Mini-HOWTO for using the earlyprintk=dbgp boot option with a
10 You need two computers, the 'USB debug key' special gadget and
11 two USB cables, connected like this::
13 [host/target] <-------> [USB debug key] <-------> [client/console]
18 a) Host/target system needs to have USB debug port capability.
21 the lspci -vvv output::
23 # lspci -vvv
25 …00:1d.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 (rev 03) (p…
27 …Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisIN…
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/linux/Documentation/devicetree/bindings/mfd/
H A Domap-usb-host.txt1 OMAP HS USB Host
5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
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/linux/drivers/phy/marvell/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Armada 375 USB cluster PHY support" if COMPILE_TEST
20 tristate "Marvell Berlin USB PHY Driver"
25 Enable this to support the USB PHY on Marvell Berlin SoCs.
56 used by various controllers (Ethernet, sata, usb, PCIe...).
67 lanes can be used by various controllers (Ethernet, sata, usb,
85 tristate "Marvell USB HSIC 28nm PHY Driver"
89 Enable this to support Marvell USB HSIC PHY driver for Marvell
91 The PHY driver will be used by Marvell ehci driver.
96 tristate "Marvell USB 2.0 28nm PHY Driver"
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/linux/Documentation/devicetree/bindings/usb/
H A Dbrcm,bcm7445-ehci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/brcm,bcm7445-ehci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB USB EHCI Controller
10 - $ref: usb-hcd.yaml
13 - Al Cooper <alcooperx@gmail.com>
17 const: brcm,bcm7445-ehci
27 description: Clock specifier for the EHCI clock
29 clock-names:
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H A Datmel-usb.txt1 Atmel SOC USB controllers
6 - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers
8 - reg: Address and length of the register set for the device
9 - interrupts: Should contain ohci interrupt
10 - clocks: Should reference the peripheral, host and system clocks
11 - clock-names: Should contain three strings
15 - num-ports: Number of ports.
16 - atmel,vbus-gpio: If present, specifies a gpio that needs to be
18 - atmel,oc-gpio: If present, specifies a gpio that needs to be
22 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
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H A Dehci-st.txt1 ST USB EHCI controller
4 - compatible : must be "st,st-ehci-300x"
5 - reg : physical base addresses of the controller and length of memory mapped
7 - interrupts : one EHCI interrupt should be described here
8 - pinctrl-names : a pinctrl state named "default" must be defined
9 - pinctrl-0 : phandle referencing pin configuration of the USB controller
10 See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
11 - clocks : phandle list of usb clocks
12 - clock-names : should be "ic" for interconnect clock and "clk48"
13 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
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H A Dmarvell,pxau2o-ehci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/marvell,pxau2o-ehci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Marvell PXA/MMP EHCI
11 - Lubomir Rintel <lkundrak@v3.sk>
14 - $ref: usb-hcd.yaml#
18 const: marvell,pxau2o-ehci
29 clock-names:
35 phy-names:
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H A Dsamsung,exynos-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/samsung,exynos-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC USB 2.0 EHCI/OHCI Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - samsung,exynos4210-ehci
16 - samsung,exynos4210-ohci
21 clock-names:
23 - const: usbhost
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H A Dnvidia,tegra20-ehci.txt1 Tegra SOC USB controllers
3 The device node for a USB controller that is part of a Tegra
9 - compatible : For Tegra20, must contain "nvidia,tegra20-ehci".
10 For Tegra30, must contain "nvidia,tegra30-ehci". Otherwise, must contain
11 "nvidia,<chip>-ehci" plus at least one of the above, where <chip> is
13 - nvidia,phy : phandle of the PHY that the controller is connected to.
14 - clocks : Must contain one entry, for the module clock.
15 See ../clocks/clock-bindings.txt for details.
16 - resets : Must contain an entry for each entry in reset-names.
18 - reset-names : Must include the following entries:
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/linux/drivers/usb/chipidea/
H A Dhost.c1 // SPDX-License-Identifier: GPL-2.0
3 * host.c - ChipIdea USB host controller driver
12 #include <linux/usb.h>
13 #include <linux/usb/hcd.h>
14 #include <linux/usb/chipidea.h>
19 #include "../host/ehci.h"
40 struct ehci_hcd *ehci in ehci_ci_portpower()
39 struct ehci_hcd *ehci = hcd_to_ehci(hcd); ehci_ci_portpower() local
87 struct ehci_hcd *ehci = hcd_to_ehci(hcd); ehci_ci_reset() local
122 struct ehci_hcd *ehci; host_start() local
249 struct ehci_hcd *ehci = hcd_to_ehci(hcd); ci_ehci_hub_control() local
331 struct ehci_hcd *ehci = hcd_to_ehci(hcd); ci_ehci_bus_suspend() local
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/linux/drivers/usb/early/
H A Dehci-dbgp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Standalone EHCI usb debug driver
21 #include <linux/usb/ch9.h>
22 #include <linux/usb/ehci_def.h>
28 #include <asm/pci-direct.h>
31 /* The code here is intended to talk directly to the EHCI debug port
32 * and does not require that you have any kind of USB host controller
33 * drivers or USB device drivers compiled into the kernel.
36 * need to pass where a USB debug device works in the following
61 static int dbgp_not_safe; /* Cannot use debug device during ehci reset */
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-pci-drivers-ehci_hcd2 /sys/bus/usb/devices/usbN/../companion
7 PCI-based EHCI USB controllers (i.e., high-speed USB-2.0
9 "companion" full/low-speed USB-1.1 controllers. When a
10 high-speed device is plugged in, the connection is routed
11 to the EHCI controller; when a full- or low-speed device
15 Sometimes you want to force a high-speed device to connect
23 For example: To force the high-speed device attached to
26 echo 4 >/sys/bus/usb/devices/usb2/../companion
28 To return the port to high-speed operation::
30 echo -4 >/sys/bus/usb/devices/usb2/../companion
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/linux/include/linux/usb/
H A Dehci_def.h1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2001-2002 by David Brownell
9 #include <linux/usb/ehci-dbgp.h>
11 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
17 * some hosts treat caplength and hciversion as parts of a 32-bit
22 #define HC_LENGTH(ehci, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \ argument
23 (ehci_big_endian_capbase(ehci) ? 24 : 0)))
24 #define HC_VERSION(ehci, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \ argument
25 (ehci_big_endian_capbase(ehci) ? 0 : 16)))
26 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
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/linux/Documentation/devicetree/bindings/mips/cavium/
H A Ductl.txt1 * UCTL USB controller glue
4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
24 compatible = "cavium,octeon-6335-uctl";
27 #address-cells = <2>;
[all …]
/linux/drivers/mfd/
H A Domap-usb-host.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
5 * Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com
15 #include <linux/dma-mapping.h>
17 #include <linux/platform_data/usb-omap.h>
23 #include "omap-usb.h"
26 #define OMAP_EHCI_DEVICE "ehci-omap"
27 #define OMAP_OHCI_DEVICE "ohci-omap3"
56 /* OMAP4-specific defines */
72 /* Values of UHH_REVISION - Note: these are not given in the TRM */
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/linux/Documentation/devicetree/bindings/powerpc/nintendo/
H A Dwii.txt11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
41 - compatible : should be "nintendo,hollywood-pi","nintendo,flipper-pi"
42 - reg : should contain the PI registers location and length
52 - #interrupt-cells : <1>
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/linux/arch/arm/boot/dts/st/
H A Dspear600.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <0>;
13 #size-cells = <0>;
16 compatible = "arm,arm926ej-s";
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "simple-bus";
32 vic0: interrupt-controller@f1100000 {
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H A Dspear13xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a9";
21 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
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/linux/arch/mips/boot/dts/brcm/
H A Dbcm7346.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
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/linux/arch/mips/alchemy/common/
H A Dusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * USB block power/access management abstraction.
8 * Au1200: one register to control access and clocks to O/EHCI, UDC and OTG
9 * as well as the PHY for EHCI and UDC.
20 #include <asm/mach-au1x00/au1000.h>
27 /* Au1000 USB block config bits */
28 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
32 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
34 /* Au1200 USB config bits */
41 #define USBCFG_ECE (1 << 17) /* EHCI clock enable */
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/linux/Documentation/devicetree/bindings/phy/
H A Drenesas,rcar-gen2-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,rcar-gen2-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen2 USB PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,usb-phy-r8a7742 # RZ/G1H
17 - renesas,usb-phy-r8a7743 # RZ/G1M
18 - renesas,usb-phy-r8a7744 # RZ/G1N
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