| /linux/drivers/clk/imx/ |
| H A D | clk-imx31.c | 35 static const char *csi_sel[] = { "upll", "spll", };
36 static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
39 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
60 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL); in _mx31_clocks_init()
66 clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5); in _mx31_clocks_init()
71 clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2); in _mx31_clocks_init()
113 clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12); in _mx31_clocks_init()
117 clk_set_parent(clk[csi], clk[upll]); in _mx31_clocks_init()
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| H A D | clk-imx25.c | 47 static const char *per_sel_clks[] = { "ahb", "upll", };
54 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
83 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL)); in __mx25_clocks_init()
88 clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6); in __mx25_clocks_init()
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| H A D | clk-imx7ulp.c | 30 …{ "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
66 hws[IMX7ULP_CLK_UPLL] = imx_get_clk_hw_by_name(np, "upll"); in imx7ulp_clk_scg1_init()
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | imx7ulp-scg-clock.yaml | 64 - const: upll
84 <&firc>, <&upll>;
86 "firc", "upll";
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| H A D | imx7ulp-pcc-clock.yaml | 71 - const: upll
108 "upll", "sosc_bus_clk", "firc_bus_clk",
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| H A D | imx31-clock.yaml | 24 upll 5
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| H A D | imx25-clock.yaml | 22 upll 3
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| /linux/drivers/clk/uniphier/ |
| H A D | clk-uniphier-sys.c | 88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
97 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
105 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
114 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
122 UNIPHIER_CLK_FACTOR("usb30-hsphy0", 16, "upll", 1, 12),
133 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
141 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
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| /linux/include/linux/clk/ |
| H A D | at91_pmc.h | 50 #define AT91_PMC_PLL_ACR_DEFAULT_UPLL UL(0x12020010) /* Default PLL ACR value for UPLL */
52 #define AT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage regulator Control */
53 #define AT91_PMC_PLL_ACR_UTMIBG (1 << 13) /* UPLL Bandgap Control */
202 #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */
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| /linux/drivers/clk/at91/ |
| H A D | pmc.h | 82 u8 upll : 1; member
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| H A D | sam9x7.c | 25 * @PLL_ID_UPLL: UPLL identifier
117 .upll = true,
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| H A D | sam9x60.c | 50 .upll = true,
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-rk3399.c | 137 PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" };
146 "npll", "upll" };
148 "upll", "xin24m" };
150 "ppll", "upll", "xin24m" };
418 MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | radeon_uvd.c | 929 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
945 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | si.c | 1694 * si_calc_upll_dividers - calc UPLL clock dividers
1710 * Calculate dividers for UVDs UPLL (except APUs).
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| /linux/drivers/clk/samsung/ |
| H A D | clk-exynos3250.c | 673 /* APLL & MPLL & BPLL & UPLL */
|