Home
last modified time | relevance | path

Searched +full:ulp +full:- +full:allow (Results 1 – 25 of 70) sorted by relevance

123

/freebsd/sys/contrib/device-tree/Bindings/input/
H A Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd/sys/dev/cxgbe/firmware/
H A Dt6fw_cfg.txt74 # ulp insert pi source info in DIF
80 # ulp insert pi source info in
86 #mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC
88 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
138 # PF4 is the resource-rich PF that the bus/nexus driver attaches to.
139 # It gets 32 MSI/128 MSI-X vectors.
175 # PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
181 # PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
202 # For Virtual functions, we only allow NIC functionality and we only allow
H A Dt6fw_cfg_fpga.txt3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
52 # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
[all …]
H A Dt6fw_cfg_uwire.txt3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
52 # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
[all …]
/freebsd/contrib/arm-optimized-routines/pl/math/include/
H A Dpl_test.h6 * Copyright (c) 2022-2023, Arm Limited.
7 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception.
10 /* Emit max ULP threshold - silenced for building the routine. */
15 build flags - defer expansion by one pass to allow those flags to be expanded
/freebsd/contrib/arm-optimized-routines/pl/math/test/
H A Dpl_test.h5 * Copyright (c) 2022-2023, Arm Limited.
6 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception.
9 /* Emit the max ULP threshold, l, for routine f. Piggy-back PL_TEST_EXPECT_FENV
21 build flags - defer expansion by one pass to allow those flags to be expanded
31 PL_TEST_INTERVAL (f, -lo, -hi, n)
35 PL_TEST_INTERVAL_C (f, -lo, -hi, n, c)
36 // clang-format off
39 // clang-format on
/freebsd/contrib/arm-optimized-routines/pl/math/
H A Dv_exp10_2u.c2 * Double-precision vector 10^x function.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
14 #define SpecialBound 306.0 /* floor (log10 (2^1023)) - 1. */
27 rel error: 0x1.5ddf8f28p-54
28 abs error: 0x1.5ed266c8p-54 in [ -log10(2)/256, log10(2)/256 ]
29 maxerr: 1.14432 +0.5 ulp. */
33 .log2_10_hi = V2 (0x1.34413509f79ffp-9), /* log2(10)/N. */
34 .log2_10_lo = V2 (-0x1.9dc1da994fd21p-66),
43 #define IndexMask v_u64 (N - 1)
47 # define TinyBound v_u64 (0x2000000000000000) /* asuint64 (0x1p-511). */
[all …]
H A Dv_exp10f_2u4.c2 * Single-precision vector 10^x function.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
27 rel error: 0x1.89dafa3p-24
28 abs error: 0x1.167d55p-23 in [-log10(2)/2, log10(2)/2]
29 maxerr: 1.85943 +0.5 ulp. */
31 V4 (0x1.2d8176p+0f), V4 (0x1.12b41ap-1f) },
35 .log10_2_and_inv = { 0x1.a934fp+1, 0x1.344136p-2, -0x1.ec10cp-27, 0 },
46 # define TinyBound v_u32 (0x20000000) /* asuint (0x1p-63). */
48 # define Thres v_u32 (0x22180000) /* BigBound - TinyBound. */
72 uint32x4_t cmp2 = vcagtq_f32 (n, d->scale_thresh); in special_case()
[all …]
H A Dv_erfcf_1u7.c2 * Single-precision vector erfc(x) function.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
24 .offset = V4 (0xb7fffd7b), /* 0xffffffff - asuint(shift) - 644. */
25 .table_scale = V4 (0x28000000 << 1), /* asuint (2^-47) << 1. */
30 .coeffs = (float32x4_t){ 0x1.555556p-2f, 0x1.555556p-1f, 0x1.111112p-3f, 0 },
31 .third = V4 (0x1.555556p-2f),
32 .two_over_five = V4 (-0x1.99999ap-2f),
33 .tenth = V4 (-0x1.99999ap-4f),
39 #define TinyBound 0x41000000 /* 0x1p-62f << 1. */
40 #define Thres 0xbe000000 /* asuint(infinity) << 1 - TinyBound. */
[all …]
H A Dv_erff_2u.c2 * Single-precision vector erf(x) function.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
19 .max = V4 (3.9375), /* 4 - 8/128. */
21 .third = V4 (0x1.555556p-2f), /* 1/3. */
23 .tiny_bound = V4 (0x1p-62f),
24 .scale_minus_one = V4 (0x1.06eba8p-3f), /* scale - 1.0. */
51 /* Single-precision implementation of vector erf(x).
54 Let d = x - r, and scale = 2 / sqrt(pi) * exp(-r^2). For x near r,
56 erf(x) ~ erf(r) + scale * d * [1 - r * d - 1/3 * d^2]
61 Maximum error: 1.93 ULP
[all …]
H A Dv_erfinvf_5u.c2 * Single-precision inverse error function (AdvSIMD variant).
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
18 formats to allow for table-based (vector-to-vector) lookup.
25 P_10 and Q_10 are also stored in homogenous vectors to allow better
35 .P29_3 = V4 (0x1.b13626p-2),
36 .tailshift = V4 (-0.87890625),
37 .Plo = { -0x1.a31268p+3, -0x1.fc0252p-4, 0x1.ac9048p+4, 0x1.119d44p+0 },
38 .PQ = { -0x1.293ff6p+3, -0x1.f59ee2p+0, -0x1.8265eep+3, -0x1.69952p-4 },
39 .Qhi = { 0x1.ef5eaep+4, 0x1.c7b7d2p-1, -0x1.12665p+4, -0x1.167d7p+1 },
40 .P_50 = { V4 (0x1.3d8948p-3), V4 (0x1.61f9eap+0), V4 (0x1.61c6bcp-1),
[all …]
H A Dv_erf_2u5.c2 * Double-precision vector erf(x) function.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
22 .third = V2 (0x1.5555555555556p-2), /* used to compute 2/3 and 1/6 too. */
23 .two_over_fifteen = V2 (0x1.1111111111111p-3),
24 .tenth = V2 (-0x1.999999999999ap-4),
25 .two_over_five = V2 (-0x1.999999999999ap-2),
26 .two_over_nine = V2 (-0x1.c71c71c71c71cp-3),
27 .two_over_fortyfive = V2 (0x1.6c16c16c16c17p-5),
28 .max = V2 (5.9921875), /* 6 - 1/128. */
32 .tiny_bound = V2 (0x1p-226),
[all …]
H A Dv_erfc_1u8.c2 * Double-precision vector erfc(x) function.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
25 Index offset is 0xffffffffffffffff - asuint64(shift) - 3487. */
27 .table_scale = V2 (0x37f0000000000000 << 1), /* asuint64 (2^-128) << 1. */
30 .p20 = V2 (0x1.5555555555555p-2), /* 1/3, used to compute 2/3 and 1/6. */
31 .p40 = V2 (-0x1.999999999999ap-4), /* 1/10. */
32 .p41 = V2 (-0x1.999999999999ap-2), /* 2/5. */
33 .p42 = V2 (0x1.1111111111111p-3), /* 2/15. */
34 .p51 = V2 (-0x1.c71c71c71c71cp-3), /* 2/9. */
35 .p52 = V2 (0x1.6c16c16c16c17p-5), /* 2/45. */
[all …]
/freebsd/sys/netpfil/ipfw/
H A Dip_fw2.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2002-2009 Luigi Rizzo, Universita` di Pisa
143 VNET_DEFINE(unsigned int, fw_tables_sets) = 0; /* Don't use set-aware tables */
203 "Rule number auto-increment step");
220 "Use per-set namespace for tables");
252 #define L3HDR(T, ip) ((T *)((u_int32_t *)(ip) + (ip)->ip_hl))
262 int type = icmp->icmp_type; in icmptype_match()
264 return (type <= ICMP_MAXTYPE && (cmd->d[0] & (1<<type)) ); in icmptype_match()
273 int type = icmp->icmp_type; in is_icmp_query()
[all …]
/freebsd/contrib/arm-optimized-routines/math/aarch64/
H A Dv_exp2f.c2 * Single-precision vector 2^x function.
4 * Copyright (c) 2019-2023, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
19 /* maxerr: 1.962 ulp. */
20 .poly = { V4 (0x1.59977ap-10f), V4 (0x1.3ce9e4p-7f), V4 (0x1.c6bd32p-5f),
21 V4 (0x1.ebf9bcp-3f), V4 (0x1.62e422p-1f) },
29 #define C(i) d->poly[i]
33 # define TinyBound v_u32 (0x20000000) /* asuint (0x1p-63). */
35 # define SpecialBound v_u32 (0x22800000) /* BigBound - TinyBound. */
58 uint32x4_t cmp2 = vcagtq_f32 (n, d->scale_thresh); in special_case()
[all …]
H A Dv_expf.c2 * Single-precision vector e^x function.
4 * Copyright (c) 2019-2023, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
20 /* maxerr: 1.45358 +0.5 ulp. */
21 .poly = { V4 (0x1.0e4020p-7f), V4 (0x1.573e2ep-5f), V4 (0x1.555e66p-3f),
22 V4 (0x1.fffdb6p-2f), V4 (0x1.ffffecp-1f) },
25 .ln2_hi = V4 (0x1.62e4p-1f),
26 .ln2_lo = V4 (0x1.7f7d1cp-20f),
34 #define C(i) d->poly[i]
38 # define TinyBound v_u32 (0x20000000) /* asuint (0x1p-63). */
[all …]
H A Dv_exp.c2 * Double-precision vector e^x function.
4 * Copyright (c) 2019-2023, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
12 #define IndexMask (N - 1)
22 /* maxerr: 1.88 +0.5 ulp
23 rel error: 1.4337*2^-53
24 abs error: 1.4299*2^-53 in [ -ln2/256, ln2/256 ]. */
25 .poly = { V2 (0x1.ffffffffffd43p-2), V2 (0x1.55555c75adbb2p-3),
26 V2 (0x1.55555da646206p-5) },
32 .ln2_hi = V2 (0x1.62e42fefa39efp-8), /* ln2/N. */
[all …]
/freebsd/contrib/gdtoa/
H A Dchanges2 dtoa.c: adjust dtoa to allow negative ndigits for modes 3,5,7,9
3 (fixed-point mode); fix rounding bug in these modes when the input
4 d (to be converted) satisfies 10^-(ndigits+1) <= |d| < 10^-ndigits ,
7 the result is empty (i.e., when |d| <= 5 * 10^-ndigits).
25 return +-Infinity for IEEE arithmetic, +- the largest machine number
30 dtoa.c: tweak strtod (one-line addition) so the end-pointer = start
35 reasonably with huge numbers and 16-bit ints.
47 < for(result_k = 0; sizeof(Bigint) - sizeof(unsigned long) + j < i;
48 ---
49 > for(result_k = 0; sizeof(Bigint) - sizeof(unsigned long) + j <= i;
[all …]
/freebsd/contrib/arm-optimized-routines/math/test/
H A Dulp.c2 * ULP error checking tool for math functions.
4 * Copyright (c) 2019-2023, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
94 if (r - m <= -n) in randn()
155 that produce dense sampling without collisions and allow in next1()
157 uint64_t r = g->start + g->off; in next1()
158 g->off += g->step + randn (g->step / 2); in next1()
159 if (g->off > g->len) in next1()
160 g->off -= g->len; /* hack. */ in next1()
168 uint64_t r = g->start + randn (g->len); in next2()
[all …]
/freebsd/lib/msun/ld80/
H A Dk_tanl.c20 * Domain [-0.67434, 0.67434], range ~[-2.25e-22, 1.921e-22]
21 * |tan(x)/x - t(x)| < 2**-71.9
28 T3hi = 0.33333333333333331, /* 0x15555555555555.0p-54 */
29 T3lo = 1.8350121769317163e-17, /* 0x15280000000000.0p-108 */
30 T5hi = 0.13333333333333336, /* 0x11111111111112.0p-55 */
31 T5lo = 1.3051083651294260e-17, /* 0x1e180000000000.0p-109 */
32 T7hi = 0.053968253968250494, /* 0x1ba1ba1ba1b827.0p-57 */
33 T7lo = 3.1509625637859973e-18, /* 0x1d100000000000.0p-111 */
34 pio4_hi = 0.78539816339744828, /* 0x1921fb54442d18.0p-53 */
35 pio4_lo = 3.0628711372715500e-17, /* 0x11a80000000000.0p-107 */
[all …]
/freebsd/lib/msun/ld128/
H A Dk_tanl.c20 * Domain [-0.67434, 0.67434], range ~[-3.37e-36, 1.982e-37]
21 * |tan(x)/x - t(x)| < 2**-117.8 (XXX should be ~1e-37)
26 T3 = 0x1.5555555555555555555555555553p-2L,
27 T5 = 0x1.1111111111111111111111111eb5p-3L,
28 T7 = 0x1.ba1ba1ba1ba1ba1ba1ba1b694cd6p-5L,
29 T9 = 0x1.664f4882c10f9f32d6bbe09d8bcdp-6L,
30 T11 = 0x1.226e355e6c23c8f5b4f5762322eep-7L,
31 T13 = 0x1.d6d3d0e157ddfb5fed8e84e27b37p-9L,
32 T15 = 0x1.7da36452b75e2b5fce9ee7c2c92ep-10L,
33 T17 = 0x1.355824803674477dfcf726649efep-11L,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCodeGenPrepare.cpp1 //===-- AMDGPUCodeGenPrepare.cpp ------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
35 #define DEBUG_TYPE "amdgpu-codegenprepare"
43 "amdgpu-codegenprepare-widen-constant-loads",
44 cl::desc("Widen sub-dword constant address space loads in AMDGPUCodeGenPrepare"),
49 "amdgpu-codegenprepare-widen-16-bit-ops",
50 cl::desc("Widen uniform 16-bit instructions to 32-bit in AMDGPUCodeGenPrepare"),
55 BreakLargePHIs("amdgpu-codegenprepare-break-large-phis",
[all …]
/freebsd/lib/msun/src/
H A Dk_tan.c12 * kernel tan function on ~[-pi/4, pi/4] (except on -0), pi/4 ~ 0.7854
15 * Input k indicates whether tan (if k = 1) or -1/tan (if k = -1) is returned.
18 * 1. Since tan(-x) = -tan(x), we need only to consider positive x.
19 * 2. Callers must return tan(-0) = -0 without calling here since our
20 * odd polynomial is not evaluated in a way that preserves -0.
28 * |tan(x) 2 4 26 | -59.2
29 * |----- - (1+T1*x +T2*x +.... +T13*x )| <= 2
41 * 4. For x in [0.67434,pi/4], let y = pi/4 - x, then
42 * tan(x) = tan(pi/4-y) = (1-tan(y))/(1+tan(y))
43 * = 1 - 2*(tan(y) - (tan(y)^2)/(1+tan(y)))
[all …]
/freebsd/sys/dev/e1000/
H A De1000_ich8lan.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
36 * 82562G-2 10/100 Network Connection
38 * 82562GT-2 10/100 Network Connection
40 * 82562V-2 10/100 Network Connection
41 * 82566DC-2 Gigabit Network Connection
43 * 82566DM-2 Gigabit Network Connection
50 * 82567LM-2 Gigabit Network Connection
51 * 82567LF-2 Gigabit Network Connection
52 * 82567V-2 Gigabit Network Connection
[all …]
/freebsd/lib/libc/xdr/
H A Dxdr.356 These routines allow C programmers to describe
57 arbitrary data structures in a machine-independent fashion.
61 .Bl -tag -width indent -compact
76 A filter primitive that translates between variable-length
236 A macro that invokes the get\-position routine
270 A macro that invokes the in-line routine associated with the
458 is non-zero.
673 .Fn xdr_u_long "XDR *xdrs" "unsigned long *ulp"
768 A filter primitive that translates between fixed-length
839 .%Q "Sun Microsystems, Inc., USC\-ISI"

123