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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dsocionext,uniphier-sd.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/socionext,uniphier-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
16 - socionext,uniphier-sd-v2.91
17 - socionext,uniphier-sd-v3.1
18 - socionext,uniphier-sd-v3.1.1
32 dma-names:
33 const: rx-tx
[all …]
H A Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - socionext,uniphier-sd4hc
19 - const: cdns,sd4hc
39 cdns,phy-input-delay-sd-highspeed:
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H A Dsdhci-sprd.txt1 * Spreadtrum SDHCI controller (sdhci-sprd)
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
16 "enable" - gate clock which used for enabling/disabling the device (required)
17 "2x_enable" - gate clock controlling the device for some special platforms (optional)
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H A Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cell
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H A Dsdhci-st.txt1 * STMicroelectronics sdhci-st MMC/SD controller
5 used by the sdhci-st driver.
8 - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
13 - clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
14 See: Documentation/devicetree/bindings/resource-names.txt
15 - clocks: Phandle to the clock.
16 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
18 - interrupts: One mmc interrupt should be described here.
19 - interrupt-names: Should be "mmcirq".
21 - pinctrl-names: A pinctrl state names "default" must be defined.
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H A Dbrcm,sdhci-brcmstb.txt4 and the properties used by the sdhci-brcmstb driver.
6 NOTE: The driver disables all UHS speed modes by default and depends
11 - compatible: should be one of the following
12 - "brcm,bcm7425-sdhci"
13 - "brcm,bcm7445-sdhci"
14 - "brcm,bcm7216-sdhci"
16 Refer to clocks/clock-bindings.txt for generic clock consumer properties.
21 sd-uhs-sdr50;
22 sd-uhs-ddr50;
23 sd-uhs-sdr104;
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H A Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
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H A Dbrcm,sdhci-brcmstb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/brcm,sdhci-brcmst
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/freebsd/sys/contrib/device-tree/src/arm64/sprd/
H A Dums512-1h10.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Unisoc UMS512-1h10 boards DTS file
8 /dts-v1/;
13 model = "Unisoc UMS512-1H10 Board";
15 compatible = "sprd,ums512-1h10", "sprd,ums512";
28 stdout-path = "serial1:115200n8";
42 bus-width = <4>;
43 no-sdio;
44 no-mmc;
45 sprd,phy-delay-sd-uhs-sdr104 = <0x7f 0x73 0x72 0x72>;
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/freebsd/sys/dev/mmc/
H A Dmmc_helpers.c44 * All UHS-I modes requires 1.8V signaling. in mmc_parse_sd_speed()
46 if (device_has_property(dev, "no-1-8-v")) in mmc_parse_sd_speed()
48 if (device_has_property(dev, "cap-sd-highspeed")) in mmc_parse_sd_speed()
49 host->caps |= MMC_CAP_HSPEED; in mmc_parse_sd_speed()
50 if (device_has_property(dev, "sd-uhs-sdr12") && !no_18v) in mmc_parse_sd_speed()
51 host->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_SIGNALING_180; in mmc_parse_sd_speed()
52 if (device_has_property(dev, "sd-uhs-sdr25") && !no_18v) in mmc_parse_sd_speed()
53 host->caps |= MMC_CAP_UHS_SDR25 | MMC_CAP_SIGNALING_180; in mmc_parse_sd_speed()
54 if (device_has_property(dev, "sd-uhs-sdr50") && !no_18v) in mmc_parse_sd_speed()
55 host->caps |= MMC_CAP_UHS_SDR50 | MMC_CAP_SIGNALING_180; in mmc_parse_sd_speed()
[all …]
H A Dbridge.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
33 * Group. This Simplified Specification is provided on a non-confidential
36 * Association, SD Group, SD-3C LLC or other third parties.
42 * is provided "AS-IS" without any representations or warranties of any
43 * kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD
45 * right of the SD Group, SD-3C LLC, the SD Card Association or any third
48 * SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing
49 * herein shall be construed as an obligation by the SD Group, the SD-3C LLC
51 * information, know-how or other confidential information to any third party.
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/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A Dmpfs-polarberry.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2022 Microchip Technology Inc */
4 /dts-v1/;
7 #include "mpfs-polarberry-fabric.dtsi"
19 stdout-path = "serial0:115200n8";
38 phy-mode = "sgmii";
39 phy-handl
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H A Dmpfs-sev-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
7 #include "mpfs-sev-kit-fabric.dtsi"
10 #address-cells = <2>;
11 #size-cells = <2>;
12 model = "Microchip PolarFire-So
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H A Dmicrochip-mpfs-icicle-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
6 #include "microchip-mpfs.dtsi"
12 model = "Microchip PolarFire-SoC Icicle Kit";
13 compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
25 stdout-path = "serial1:115200n8";
29 timebase-frequency = <RTCCLK_FREQ>;
48 clock-frequency = <125000000>;
70 bus-width = <4>;
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H A Dmpfs-m100pfsevp.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Original all-in-one devicetree:
4 * Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries-embedded.de>
6 * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
8 /dts-v
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H A Dmpfs-icicle-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
7 #include "mpfs-icicle-kit-fabric.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-binding
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1012a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "fsl-ls1012a.dtsi"
15 compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
29 sd-uhs-sdr104;
30 sd-uhs-sdr50;
31 sd-uhs-sdr25;
32 sd-uhs-sdr12;
37 mmc-hs200-1_8v;
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H A Dfsl-lx2160a-clearfog-itx.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
10 #include "fsl-lx2160a-cex7.dtsi"
11 #include <dt-bindings/input/linux-event-codes.h>
20 stdout-path = "serial0:115200n8";
23 gpio-keys {
24 compatible = "gpio-keys";
28 linux,can-disable;
34 sfp0: sfp-0 {
36 i2c-bus = <&sfp0_i2c>;
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H A Dfsl-ls1046a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
6 * Copyright 2019-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1046a.dtsi"
17 compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
27 stdout-path = "serial0:115200n8";
40 mmc-hs200-1_8v;
41 sd-uhs-sdr104;
42 sd-uhs-sdr50;
[all …]
H A Dfsl-lx2160a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2018-2020 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3288-veyron-sdmmc.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
15 sdcard-supply = <&vccio_sd>;
24 sdmmc_bus4: sdmmc-bus4 {
31 sdmmc_clk: sdmmc-clk {
35 sdmmc_cmd: sdmmc-cmd {
45 sdmmc_cd_disabled: sdmmc-cd-disabled {
50 sdmmc_cd_pin: sdmmc-cd-pin {
57 vcc9-supply = <&vcc_5v>;
61 regulator-name = "vccio_sd";
62 regulator-min-microvolt = <1800000>;
[all …]
H A Drv1126-edgeble-neu2-io.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "rv1126-edgeble-neu2.dtsi"
13 compatible = "edgeble,neural-compute-module-2-i
[all...]
H A Drk3288-phycore-rdk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device tree file for Phytec PCM-947 carrier board
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/leds-pca9532.h>
12 #include "rk3288-phycore-som.dtsi"
15 model = "Phytec RK3288 PCM-947";
16 compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
18 user_buttons: user-buttons {
19 compatible = "gpio-keys";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstih410-b2120.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include "stihxxx-b2120.dtsi"
11 compatible = "st,stih410-b2120", "st,stih410";
14 stdout-path = &sbc_serial0;
38 max-frequency = <200000000>;
39 sd-uhs-sdr50;
40 sd-uhs-sdr104;
41 sd-uhs-ddr50;
60 sti-display-subsystem@0 {
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H A Dstih418-b2199.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "st,stih418-b2199", "st,stih418";
14 stdout-path = &sbc_serial0;
28 compatible = "gpio-leds";
29 led-red {
32 linux,default-trigger = "heartbeat";
34 led-green {
36 default-state = "off";
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