| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | qcom,sm8250-pinctrl.yaml | 64 - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
118 gpio-ranges = <&tlmm 0 0 181>; /* GPIOs + ufs_reset */
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| H A D | qcom,sm6375-tlmm.yaml | 56 - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
121 gpio-ranges = <&tlmm 0 0 157>; /* GPIOs + ufs_reset */
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| H A D | qcom,qcs8300-tlmm.yaml | 61 - enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ]
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| H A D | qcom,qcs615-tlmm.yaml | 69 sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
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| H A D | qcom,sm6115-tlmm.yaml | 61 sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
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| H A D | qcom,sdm670-tlmm.yaml | 58 - enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
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| H A D | qcom,milos-tlmm.yaml | 61 - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
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| H A D | qcom,maili-tlmm.yaml | 61 - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
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| H A D | qcom,sc7280-pinctrl.yaml | 60 sdc2_cmd, sdc2_data, ufs_reset ]
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| H A D | qcom,sm8650-tlmm.yaml | 61 - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
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| H A D | qcom,sm8450-tlmm.yaml | 61 - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
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| H A D | qcom,sm8350-tlmm.yaml | 114 gpio-ranges = <&tlmm 0 0 204>; /* GPIOs + ufs_reset */
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| H A D | qcom,sm8550-tlmm.yaml | 61 - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
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| H A D | qcom,sm7150-tlmm.yaml | 69 sdc2_cmd, sdc2_data, ufs_reset ]
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| H A D | qcom,sc8180x-tlmm.yaml | 62 - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
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| H A D | qcom,sm8750-tlmm.yaml | 61 - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
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| H A D | qcom,kaanapali-tlmm.yaml | 61 - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
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| H A D | qcom,sc8280xp-tlmm.yaml | 56 - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ]
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| H A D | qcom,x1e80100-tlmm.yaml | 61 - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
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| H A D | qcom,sdx65-tlmm.yaml | 53 … - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, sdc1_rclk ]
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| /linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-qmp-ufs.c | 1207 struct reset_control *ufs_reset; member
2095 ret = reset_control_assert(qmp->ufs_reset); in qmp_ufs_phy_calibrate()
2101 ret = reset_control_deassert(qmp->ufs_reset); in qmp_ufs_phy_calibrate()
2169 if (!qmp->ufs_reset) { in qmp_ufs_phy_init()
2170 qmp->ufs_reset = in qmp_ufs_phy_init()
2173 if (IS_ERR(qmp->ufs_reset)) { in qmp_ufs_phy_init()
2174 ret = PTR_ERR(qmp->ufs_reset); in qmp_ufs_phy_init()
2176 qmp->ufs_reset = NULL; in qmp_ufs_phy_init()
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| /linux/drivers/pinctrl/qcom/ |
| H A D | pinctrl-sc8280xp.c | 76 #define UFS_RESET(pg_name, offset) \ macro
328 PINCTRL_PIN(228, "UFS_RESET"),
1865 [228] = UFS_RESET(ufs_reset, 0xf1000),
1866 [229] = UFS_RESET(ufs1_reset, 0xf3000),
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| H A D | pinctrl-maili.c | 81 #define UFS_RESET(pg_name, ctl, io) \ macro
332 PINCTRL_PIN(226, "UFS_RESET"),
1555 [226] = UFS_RESET(ufs_reset, 0xf1004, 0xf2000),
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| H A D | pinctrl-x1e80100.c | 79 #define UFS_RESET(pg_name, offset) \ macro
342 PINCTRL_PIN(238, "UFS_RESET"),
1805 [238] = UFS_RESET(ufs_reset, 0xf9000),
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