1*e7db6f15SJingyi Wang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*e7db6f15SJingyi Wang%YAML 1.2 3*e7db6f15SJingyi Wang--- 4*e7db6f15SJingyi Wang$id: http://devicetree.org/schemas/pinctrl/qcom,kaanapali-tlmm.yaml# 5*e7db6f15SJingyi Wang$schema: http://devicetree.org/meta-schemas/core.yaml# 6*e7db6f15SJingyi Wang 7*e7db6f15SJingyi Wangtitle: Qualcomm Technologies, Inc. Kaanapali TLMM block 8*e7db6f15SJingyi Wang 9*e7db6f15SJingyi Wangmaintainers: 10*e7db6f15SJingyi Wang - Jingyi Wang <jingyi.wang@oss.qualcomm.com> 11*e7db6f15SJingyi Wang 12*e7db6f15SJingyi Wangdescription: 13*e7db6f15SJingyi Wang Top Level Mode Multiplexer pin controller in Qualcomm Kaanapali SoC. 14*e7db6f15SJingyi Wang 15*e7db6f15SJingyi WangallOf: 16*e7db6f15SJingyi Wang - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 17*e7db6f15SJingyi Wang 18*e7db6f15SJingyi Wangproperties: 19*e7db6f15SJingyi Wang compatible: 20*e7db6f15SJingyi Wang const: qcom,kaanapali-tlmm 21*e7db6f15SJingyi Wang 22*e7db6f15SJingyi Wang reg: 23*e7db6f15SJingyi Wang maxItems: 1 24*e7db6f15SJingyi Wang 25*e7db6f15SJingyi Wang interrupts: 26*e7db6f15SJingyi Wang maxItems: 1 27*e7db6f15SJingyi Wang 28*e7db6f15SJingyi Wang gpio-reserved-ranges: 29*e7db6f15SJingyi Wang minItems: 1 30*e7db6f15SJingyi Wang maxItems: 109 31*e7db6f15SJingyi Wang 32*e7db6f15SJingyi Wang gpio-line-names: 33*e7db6f15SJingyi Wang maxItems: 217 34*e7db6f15SJingyi Wang 35*e7db6f15SJingyi WangpatternProperties: 36*e7db6f15SJingyi Wang "-state$": 37*e7db6f15SJingyi Wang oneOf: 38*e7db6f15SJingyi Wang - $ref: "#/$defs/qcom-kaanapali-tlmm-state" 39*e7db6f15SJingyi Wang - patternProperties: 40*e7db6f15SJingyi Wang "-pins$": 41*e7db6f15SJingyi Wang $ref: "#/$defs/qcom-kaanapali-tlmm-state" 42*e7db6f15SJingyi Wang additionalProperties: false 43*e7db6f15SJingyi Wang 44*e7db6f15SJingyi Wang$defs: 45*e7db6f15SJingyi Wang qcom-kaanapali-tlmm-state: 46*e7db6f15SJingyi Wang type: object 47*e7db6f15SJingyi Wang description: 48*e7db6f15SJingyi Wang Pinctrl node's client devices use subnodes for desired pin configuration. 49*e7db6f15SJingyi Wang Client device subnodes use below standard properties. 50*e7db6f15SJingyi Wang $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 51*e7db6f15SJingyi Wang unevaluatedProperties: false 52*e7db6f15SJingyi Wang 53*e7db6f15SJingyi Wang properties: 54*e7db6f15SJingyi Wang pins: 55*e7db6f15SJingyi Wang description: 56*e7db6f15SJingyi Wang List of gpio pins affected by the properties specified in this 57*e7db6f15SJingyi Wang subnode. 58*e7db6f15SJingyi Wang items: 59*e7db6f15SJingyi Wang oneOf: 60*e7db6f15SJingyi Wang - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-6])$" 61*e7db6f15SJingyi Wang - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] 62*e7db6f15SJingyi Wang minItems: 1 63*e7db6f15SJingyi Wang maxItems: 36 64*e7db6f15SJingyi Wang 65*e7db6f15SJingyi Wang function: 66*e7db6f15SJingyi Wang description: 67*e7db6f15SJingyi Wang Specify the alternative function to be configured for the specified 68*e7db6f15SJingyi Wang pins. 69*e7db6f15SJingyi Wang enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0, 70*e7db6f15SJingyi Wang audio_ext_mclk1, audio_ref_clk, cam_asc_mclk2, cam_asc_mclk4, 71*e7db6f15SJingyi Wang cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer, 72*e7db6f15SJingyi Wang cmu_rng, coex_uart1_rx, coex_uart1_tx, coex_uart2_rx, 73*e7db6f15SJingyi Wang coex_uart2_tx, dbg_out_clk, ddr_bist_complete, ddr_bist_fail, 74*e7db6f15SJingyi Wang ddr_bist_start, ddr_bist_stop, ddr_pxi0, ddr_pxi1, ddr_pxi2, 75*e7db6f15SJingyi Wang ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0, 76*e7db6f15SJingyi Wang gnss_adc1, i2chub0_se0, i2chub0_se1, i2chub0_se2, i2chub0_se3, 77*e7db6f15SJingyi Wang i2chub0_se4, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, 78*e7db6f15SJingyi Wang i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist, 79*e7db6f15SJingyi Wang mdp_esync0_out, mdp_esync1_out, mdp_vsync, mdp_vsync0_out, 80*e7db6f15SJingyi Wang mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, 81*e7db6f15SJingyi Wang mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3, 82*e7db6f15SJingyi Wang pcie0_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux, 83*e7db6f15SJingyi Wang prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, 84*e7db6f15SJingyi Wang qdss_gpio_traceclk, qdss_gpio_tracectl, qdss_gpio_tracedata, 85*e7db6f15SJingyi Wang qlink_big_enable, qlink_big_request, qlink_little_enable, 86*e7db6f15SJingyi Wang qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3, 87*e7db6f15SJingyi Wang qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, 88*e7db6f15SJingyi Wang qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, 89*e7db6f15SJingyi Wang qup2_se2, qup2_se3, qup2_se4, qup3_se0, qup3_se1, qup3_se2, 90*e7db6f15SJingyi Wang qup3_se3, qup3_se4, qup3_se5, qup4_se0, qup4_se1, qup4_se2, 91*e7db6f15SJingyi Wang qup4_se3, qup4_se4, sd_write_protect, sdc40, sdc41, sdc42, sdc43, 92*e7db6f15SJingyi Wang sdc4_clk, sdc4_cmd, sys_throttle, tb_trig_sdc2, tb_trig_sdc4, 93*e7db6f15SJingyi Wang tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1, 94*e7db6f15SJingyi Wang tsense_pwm2, tsense_pwm3, tsense_pwm4, tsense_pwm5, tsense_pwm6, 95*e7db6f15SJingyi Wang tsense_pwm7, uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk, 96*e7db6f15SJingyi Wang uim1_data, uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1, 97*e7db6f15SJingyi Wang vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ] 98*e7db6f15SJingyi Wang 99*e7db6f15SJingyi Wang required: 100*e7db6f15SJingyi Wang - pins 101*e7db6f15SJingyi Wang 102*e7db6f15SJingyi Wangrequired: 103*e7db6f15SJingyi Wang - compatible 104*e7db6f15SJingyi Wang - reg 105*e7db6f15SJingyi Wang 106*e7db6f15SJingyi WangunevaluatedProperties: false 107*e7db6f15SJingyi Wang 108*e7db6f15SJingyi Wangexamples: 109*e7db6f15SJingyi Wang - | 110*e7db6f15SJingyi Wang #include <dt-bindings/interrupt-controller/arm-gic.h> 111*e7db6f15SJingyi Wang 112*e7db6f15SJingyi Wang tlmm: pinctrl@f100000 { 113*e7db6f15SJingyi Wang compatible = "qcom,kaanapali-tlmm"; 114*e7db6f15SJingyi Wang reg = <0x0f100000 0x300000>; 115*e7db6f15SJingyi Wang interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 116*e7db6f15SJingyi Wang gpio-controller; 117*e7db6f15SJingyi Wang #gpio-cells = <2>; 118*e7db6f15SJingyi Wang gpio-ranges = <&tlmm 0 0 218>; 119*e7db6f15SJingyi Wang interrupt-controller; 120*e7db6f15SJingyi Wang #interrupt-cells = <2>; 121*e7db6f15SJingyi Wang 122*e7db6f15SJingyi Wang qup-uart7-state { 123*e7db6f15SJingyi Wang pins = "gpio62", "gpio63"; 124*e7db6f15SJingyi Wang function = "qup1_se7"; 125*e7db6f15SJingyi Wang }; 126*e7db6f15SJingyi Wang }; 127*e7db6f15SJingyi Wang... 128