Home
last modified time | relevance | path

Searched +full:uart2 +full:- +full:pins (Results 1 – 25 of 606) sorted by relevance

12345678910>>...25

/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
11 Available mpp pins/groups and functions:
16 name pins functions
18 mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
20 mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
22 mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
[all …]
H A Dpinctrl-sirf.txt4 - compatible : "sirf,prima2-pinctrl"
5 - reg : Address range of the pinctrl registers
6 - interrupts : Interrupts used by every GPIO group
7 - gpio-controller : Indicates this device is a GPIO controller
8 - interrupt-controller : Marks the device node as an interrupt controller
10 - sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m
11 - sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m
13 Please refer to pinctrl-bindings.txt in this directory for details of the common
17 Each of these subnodes represents some desired configuration for a group of pins.
19 Required subnode-properties:
[all …]
H A Dmicrochip,pic32-pinctrl.txt3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
7 PIC32 'pin configuration node' is a node of a group of pins which can be
9 pins, optional function, and optional mux related configuration.
12 - compatible: "microchip,pic32mada-pinctrl"
13 - reg: Address range of the pinctrl registers.
14 - clocks: Clock specifier (see clock bindings for details)
16 Required properties for pin configuration sub-nodes:
17 - pins: List of pins to which the configuration applies.
19 Optional properties for pin configuration sub-nodes:
[all …]
H A Dmediatek,mt7621-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7621-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
16 pins is not supported. There is no pinconf support.
20 const: ralink,mt7621-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
[all …]
H A Dcirrus,lochnagar.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of various
26 [2] Pinctrl: ../pinctrl/pinctrl-bindings.txt
29 [3] include/dt-bindings/pinctrl/lochnagar.h
37 - cirrus,lochnagar-pinctrl
39 gpio-controller: true
41 '#gpio-cells':
[all …]
H A Dactions,s900-pinctrl.txt7 - compatible: Should be "actions,s900-pinctrl"
8 - reg: Should contain the register base address and size of
10 - clocks: phandle of the clock feeding the pin controller
11 - gpio-controller: Marks the device node as a GPIO controller.
12 - gpio-ranges: Specifies the mapping between gpio controller and
13 pin-controller pins.
14 - #gpio-cells: Should be two. The first cell is the gpio pin number
16 - interrupt-controller: Marks the device node as an interrupt controller.
17 - #interrupt-cells: Specifies the number of cells needed to encode an
21 bindings/interrupt-controller/interrupts.txt
[all …]
H A Dmediatek,mt7986-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
13 The MediaTek's MT7986 Pin controller is used to control SoC pins.
18 - mediatek,mt7986a-pinctrl
19 - mediatek,mt7986b-pinctrl
25 reg-names:
27 - const: gpio
[all …]
H A Dmscc,ocelot-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
16 - microchip,lan966x-pinctrl
17 - microchip,sparx5-pinctrl
18 - mscc,jaguar2-pinctrl
19 - mscc,luton-pinctrl
[all …]
H A Drockchip,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
18 Please refer to pinctrl-bindings.txt in this directory for details of the
22 The Rockchip pin configuration node is a node of a group of pins which can be
24 config of the pins in that group. The 'pins' selects the function mode
26 various pad settings such as pull-up, etc.
28 The pins are grouped into up to 9 individual pin banks which need to be
29 defined as gpio sub-nodes of the pinmux controller.
[all …]
/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc4337-ciaa.dts2 * CIAA NXP LPC4337 (http://www.proyecto-ciaa.com.ar)
4 * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar
9 * Released under the terms of 3-clause BSD License
12 /dts-v1/;
17 #include "dt-bindings/gpio/gpio.h"
24 serial0 = &uart2;
30 stdout-path = &uart2;
40 enet_rmii_pins: enet-rmii-pins {
42 pins = "p1_15", "p0_0";
44 slew-rate = <1>;
[all …]
H A Dlpc4357-myd-lpc4357.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel
5 * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
8 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "myir,myd-lpc4357", "nxp,lpc4357";
20 stdout-path = "serial3:115200n8";
29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&led_pins>;
[all …]
/linux/arch/mips/boot/dts/mscc/
H A Djaguar2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
13 serial1 = &uart2;
18 #address-cells = <1>;
19 #size-cells = <0>;
29 cpuintc: interrupt-controller {
30 #address-cells = <0>;
31 #interrupt-cells = <1>;
32 interrupt-controller;
[all …]
H A Dserval.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
28 cpuintc: interrupt-controller {
29 #address-cells = <0>;
30 #interrupt-cells = <1>;
31 interrupt-controller;
32 compatible = "mti,cpu-interrupt-controller";
[all …]
/linux/arch/mips/boot/dts/pic32/
H A Dpic32mzda_sk.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
14 compatible = "microchip,pic32mzda-sk", "microchip,pic32mzda";
27 compatible = "gpio-leds";
28 pinctrl-names = "default";
29 pinctrl-0 = <&user_leds_s0>;
31 led-1 {
34 linux,default-trigger = "heartbeat";
[all …]
/linux/arch/arm64/boot/dts/toshiba/
H A Dtmpv7708_pins.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 spi0_pins: spi0-pins {
8 spi1_pins: spi1-pins {
12 spi2_pins: spi2-pins {
16 spi3_pins: spi3-pins {
20 spi4_pins: spi4-pins {
24 spi5_pins: spi5-pins {
28 spi6_pins: spi6-pins {
32 uart0_pins: uart0-pins {
36 uart1_pins: uart1-pins {
[all …]
/linux/arch/mips/boot/dts/ralink/
H A Dmt7628a.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "ralink,mt7628a-soc";
9 #address-cells = <1>;
10 #size-cells = <0>;
19 resetc: reset-controller {
20 compatible = "ralink,rt2880-reset";
21 #reset-cells = <1>;
24 cpuintc: interrupt-controller {
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-ccimx6ulsbcpro.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
13 #include "imx6ul-ccimx6ulsom.dtsi"
20 compatible = "pwm-backlight";
22 brightness-levels = <0 4 8 16 32 64 128 255>;
23 default-brightness-level = <6>;
29 power-supply = <&ldo4_ext>;
34 remote-endpoint = <&display_out>;
[all …]
/linux/arch/mips/boot/dts/mobileye/
H A Deyeq6h-pins.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
9 * [0] | MUX_SEL | 0 - GPIO, 1 - alternative func
14 * [13:12] | PUD | pull-up/pull-down. 0, 3 - no, 1 - PD, 2 - PU
20 // TODO: use pinctrl-single,bias-pullup
21 // TODO: use pinctrl-single,bias-pulldown
22 // TODO: use pinctrl-single,drive-strength
23 // TODO: use pinctrl-single,input-schmitt
25 i2c0_pins: i2c0-pins {
26 pinctrl-single,pins = <
31 i2c1_pins: i2c1-pins {
[all …]
H A Deyeq5-pins.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
9 timer0_pins: timer0-pins {
11 pins = "PA0", "PA1";
13 timer1_pins: timer1-pins {
15 pins = "PA2", "PA3";
17 timer2_pins: timer2-pins {
19 pins = "PA4", "PA5";
21 pps0_pins: pps0-pin {
23 pins = "PA4";
25 pps1_pins: pps1-pin {
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 #include "armada-370-xp.dtsi"
19 #address-cells = <2>;
20 #size-cells = <2>;
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
26 serial2 = &uart2;
31 compatible = "marvell,armadaxp-mbus", "simple-bus";
38 internal-regs {
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap4-panda-es.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "omap4-panda-common.dtsi"
11 model = "TI OMAP4 PandaBoard-ES";
12 compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4";
20 ti,audio-routing =
33 pinctrl-single,pins = <
41 led_gpio_pins: gpio-led-pmx-pins {
42 pinctrl-single,pins = <
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-icore-mx8mm-ctouch2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "imx8mm-icore-mx8mm.dtsi"
14 compatible = "engicam,icore-mx8mm-ctouch2", "engicam,icore-mx8mm",
18 stdout-path = &uart2;
27 clock-frequency = <400000>;
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_i2c2>;
34 clock-frequency = <100000>;
35 pinctrl-names = "default";
[all …]
H A Dimx8mm-icore-mx8mm-edimm2.2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "imx8mm-icore-mx8mm.dtsi"
14 compatible = "engicam,icore-mx8mm-edimm2.2", "engicam,icore-mx8mm",
18 stdout-path = &uart2;
27 clock-frequency = <400000>;
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_i2c2>;
34 clock-frequency = <100000>;
35 pinctrl-names = "default";
[all …]
H A Dimx8mm-emtop-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/usb/pd.h>
15 model = "Emtop Embedded Solutions i.MX8M Mini SOM-IMX8MMLPD4 SoM";
16 compatible = "ees,imx8mm-emtop-som", "fsl,imx8mm";
19 stdout-path = &uart2;
23 compatible = "gpio-leds";
24 pinctrl-names = "default";
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7986a-rfb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/pinctrl/mt65xx.h>
14 chassis-type = "embedded";
15 compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
22 stdout-path = "serial0:115200n8";
30 reg_1p8v: regulator-1p8v {
31 compatible = "regulator-fixed";
32 regulator-name = "fixed-1.8V";
33 regulator-min-microvolt = <1800000>;
[all …]

12345678910>>...25