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/linux/arch/arm64/boot/dts/nuvoton/
H A Dma35d1-som-256m.dts1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Shan-Chun Hung <schung@nuvoton.com>
8 /dts-v1/;
12 model = "Nuvoton MA35D1-SOM";
13 compatible = "nuvoton,ma35d1-som", "nuvoton,ma35d1";
17 serial11 = &uart11;
24 stdout-path = "serial0:115200n8";
32 clk_hxt: clock-hxt {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Daspeed,ast2600-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/aspeed,ast2600-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
16 - compatible: Should be one of the following:
17 "aspeed,ast2600-scu", "syscon", "simple-mfd"
29 const: aspeed,ast2600-pinctrl
32 $ref: pinmux-node.yaml#
38 - ADC0
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H A Dnuvoton,ma35d1-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nuvoton,ma35d1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shan-Chun Hung <schung@nuvoton.com>
11 - Jacky Huang <ychuang3@nuvoton.com>
14 - $ref: pinctrl.yaml#
19 - nuvoton,ma35d1-pinctrl
24 '#address-cells':
27 '#size-cells':
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H A Dbitmain,bm1880-pinctrl.txt7 - compatible: Should be "bitmain,bm1880-pinctrl"
8 - reg: Offset and length of pinctrl space in SCTRL.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
16 pin, a group, or a list of pins or groups. This configuration for BM1880 SoC
17 includes pinmux and various pin configuration parameters, such as pull-up,
24 The following generic properties as defined in pinctrl-bindings.txt are valid
29 - pins: An array of strings, each string containing the name of a pin.
30 Valid values for pins are:
32 MIO0 - MIO111
34 - groups: An array of strings, each string containing the name of a pin
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/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov920-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAutov920 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov920 SoC pin-mux and pin-config options are listed as
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 gpa0: gpa0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
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H A Dexynosautov9-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as
11 #include "exynos-pinctrl.h"
14 gpa0: gpa0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
17 interrupt-controller;
18 #interrupt-cells = <2>;
19 interrupt-parent = <&gic>;
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/linux/drivers/pinctrl/
H A Dpinctrl-bm1880.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <linux/pinctrl/pinconf-generic.h>
20 #include "pinctrl-utils.h"
25 * struct bm1880_pinctrl - driver data
45 * struct bm1880_pctrl_group - pinctrl group
47 * @pins: Array of pins belonging to this group
48 * @npins: Number of @pins
52 const unsigned int *pins; member
57 * struct bm1880_pinmux_function - a pinmux function
75 * struct bm1880_pinconf_data - pinconf data
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/linux/arch/arm/boot/dts/st/
H A Dstih407-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "st-pincfg.h"
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 /* 0-5: PIO_SBC */
18 /* 10-19: PIO_FRONT0 */
31 /* 30-35: PIO_REAR */
38 /* 40-42: PIO_FLASH */
45 pin-controller-sbc@961f080 {
46 #address-cells = <1>;
47 #size-cells = <1>;
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/linux/arch/arm64/boot/dts/exynos/google/
H A Dgs101-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * GS101 SoC pin-mux and pin-config device tree source
5 * Copyright 2019-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
9 #include "gs101-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
15 interrupt-controller;
16 #interrupt-cells = <2>;
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/linux/drivers/pinctrl/aspeed/
H A Dpinctrl-aspeed-g6.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include "../pinctrl-utils.h"
18 #include "pinctrl-aspeed.h"
20 #define SCU400 0x400 /* Multi-function Pin Control #1 */
21 #define SCU404 0x404 /* Multi-function Pin Control #2 */
22 #define SCU40C 0x40C /* Multi-function Pin Control #3 */
23 #define SCU410 0x410 /* Multi-function Pin Control #4 */
24 #define SCU414 0x414 /* Multi-function Pin Control #5 */
25 #define SCU418 0x418 /* Multi-function Pin Control #6 */
26 #define SCU41C 0x41C /* Multi-function Pin Control #7 */
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