Lines Matching +full:uart11 +full:- +full:pins
1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include "../pinctrl-utils.h"
18 #include "pinctrl-aspeed.h"
20 #define SCU400 0x400 /* Multi-function Pin Control #1 */
21 #define SCU404 0x404 /* Multi-function Pin Control #2 */
22 #define SCU40C 0x40C /* Multi-function Pin Control #3 */
23 #define SCU410 0x410 /* Multi-function Pin Control #4 */
24 #define SCU414 0x414 /* Multi-function Pin Control #5 */
25 #define SCU418 0x418 /* Multi-function Pin Control #6 */
26 #define SCU41C 0x41C /* Multi-function Pin Control #7 */
27 #define SCU430 0x430 /* Multi-function Pin Control #8 */
28 #define SCU434 0x434 /* Multi-function Pin Control #9 */
29 #define SCU438 0x438 /* Multi-function Pin Control #10 */
30 #define SCU440 0x440 /* USB Multi-function Pin Control #12 */
31 #define SCU450 0x450 /* Multi-function Pin Control #14 */
32 #define SCU454 0x454 /* Multi-function Pin Control #15 */
33 #define SCU458 0x458 /* Multi-function Pin Control #16 */
34 #define SCU4B0 0x4B0 /* Multi-function Pin Control #17 */
35 #define SCU4B4 0x4B4 /* Multi-function Pin Control #18 */
36 #define SCU4B8 0x4B8 /* Multi-function Pin Control #19 */
37 #define SCU4BC 0x4BC /* Multi-function Pin Control #20 */
38 #define SCU4D4 0x4D4 /* Multi-function Pin Control #22 */
39 #define SCU4D8 0x4D8 /* Multi-function Pin Control #23 */
42 #define SCU610 0x610 /* Disable GPIO Internal Pull-Down #0 */
43 #define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */
44 #define SCU618 0x618 /* Disable GPIO Internal Pull-Down #2 */
45 #define SCU61C 0x61c /* Disable GPIO Internal Pull-Down #3 */
46 #define SCU630 0x630 /* Disable GPIO Internal Pull-Down #4 */
47 #define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */
48 #define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */
49 #define SCU690 0x690 /* Multi-function Pin Control #24 */
50 #define SCU694 0x694 /* Multi-function Pin Control #25 */
51 #define SCU69C 0x69C /* Multi-function Pin Control #27 */
52 #define SCU6D0 0x6D0 /* Multi-function Pin Control #29 */
923 SIG_EXPR_LIST_DECL_SESG(P23, TXD11, UART11, SIG_DESC_SET(SCU430, 22));
927 SIG_EXPR_LIST_DECL_SESG(T24, RXD11, UART11, SIG_DESC_SET(SCU430, 23));
930 FUNC_GROUP_DECL(UART11, P23, T24);
1532 * following 4 pins
1639 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */
2123 ASPEED_PINCTRL_GROUP(UART11),
2342 ASPEED_PINCTRL_FUNC(UART11),
2640 * aspeed_g6_sig_expr_set() - Configure a pin's signal by applying an
2659 for (i = 0; i < expr->ndescs; i++) { in aspeed_g6_sig_expr_set()
2660 const struct aspeed_sig_desc *desc = &expr->descs[i]; in aspeed_g6_sig_expr_set()
2661 u32 pattern = enable ? desc->enable : desc->disable; in aspeed_g6_sig_expr_set()
2662 u32 val = (pattern << __ffs(desc->mask)); in aspeed_g6_sig_expr_set()
2665 if (!ctx->maps[desc->ip]) in aspeed_g6_sig_expr_set()
2666 return -ENODEV; in aspeed_g6_sig_expr_set()
2668 WARN_ON(desc->ip != ASPEED_IP_SCU); in aspeed_g6_sig_expr_set()
2669 is_strap = desc->reg == SCU500 || desc->reg == SCU510; in aspeed_g6_sig_expr_set()
2678 * The strapping registers implement write-1-clear in aspeed_g6_sig_expr_set()
2682 u32 clear = ~val & desc->mask; in aspeed_g6_sig_expr_set()
2683 u32 w1c = desc->reg + 4; in aspeed_g6_sig_expr_set()
2686 ret = regmap_update_bits(ctx->maps[desc->ip], in aspeed_g6_sig_expr_set()
2687 w1c, desc->mask, in aspeed_g6_sig_expr_set()
2691 ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg, in aspeed_g6_sig_expr_set()
2692 desc->mask, val); in aspeed_g6_sig_expr_set()
2702 return -EPERM; in aspeed_g6_sig_expr_set()
2708 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
2710 { PIN_CONFIG_BIAS_PULL_UP, -1, 0, BIT_MASK(0)},
2711 { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
2725 .pins = aspeed_g6_pins,
2767 .name = "aspeed-g6-pinctrl",
2768 .pins = aspeed_g6_pins,
2787 { .compatible = "aspeed,ast2600-pinctrl", },
2794 .name = "aspeed-g6-pinctrl",