Home
last modified time | relevance | path

Searched +full:tx +full:- +full:ts +full:- +full:max (Results 1 – 25 of 101) sorted by relevance

12345

/linux/Documentation/devicetree/bindings/ata/
H A Dbaikal,bt1-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 SoC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
14 DWC AHCI SATA v4.10a IP-core.
17 - $ref: snps,dwc-ahci-common.yaml#
21 const: baikal,bt1-ahci
[all …]
H A Dsnps,dwc-ahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Serge Semin <fancer.lancer@gmail.com>
19 - $ref: ahci-common.yaml#
31 PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
36 clock-names:
41 - description: Application APB/AHB/AXI BIU clock
43 - pclk
[all …]
H A Dsnps,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Serge Semin <fancer.lancer@gmail.com>
20 - snps,dwc-ahci
21 - snps,spear-ahci
23 - compatible
26 - $ref: snps,dwc-ahci-common.yaml#
31 - description: Synopsys AHCI SATA-compatible devices
[all …]
/linux/drivers/net/wireless/ath/ath5k/
H A Ddesc.c2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
34 * Here we handle the processing of the low-level hw descriptors
35 * that hw reads and writes via DMA for each TX and RX attempt (that means
36 * we can also have descriptors for failed TX/RX tries). We have two kind of
37 * descriptors for RX and TX, control descriptors tell the hw how to send or
49 * TX Control descriptors *
53 * ath5k_hw_setup_2word_tx_desc() - Initialize a 2-word tx control descriptor
60 * @tx_power: Tx power in 0.5dB steps
[all …]
H A Dbase.c1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
20 * 3. Neither the names of the above-listed copyright holders nor the names
47 #include <linux/dma-mapping.h>
205 tsf -= 0x8000; in ath5k_extend_tsf()
256 struct ath5k_hw *ah = hw->priv; in ath5k_reg_notifier()
285 /* UNII-3 */ in ath5k_is_standard_channel()
287 /* 802.11j 5.030-5.080 GHz (20MHz) */ in ath5k_is_standard_channel()
296 unsigned int mode, unsigned int max) in ath5k_setup_channels() argument
[all …]
/linux/drivers/input/touchscreen/
H A Dads7846.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * - corgi_ts.c
11 * Copyright (C) 2004-2005 Richard Purdie
12 * - omap_ts.[hc], ads7846.h, ts_osk.c
39 * Support for ads7843 tested on Atmel at91sam926x-EK.
53 * note. The strength of filtering can be set in the board-* specific
76 * driver is used with DMA-based SPI controllers (like atmel_spi) on
77 * systems where main memory is not DMA-coherent (most non-x86 boards).
86 struct ads7846_buf *tx; member
152 /* leave chip selected when we're done, for quicker re-select? */
[all …]
/linux/arch/arm/boot/dts/st/
H A Dspear1310-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 compatible = "st,spear1310-evb", "st,spear1310";
14 #address-cells = <1>;
15 #size-cells = <1>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>;
63 smi-pmx {
127 label = "u-boot";
149 compatible = "gpio-keys";
[all …]
H A Dspear1340-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 compatible = "st,spear1340-evb", "st,spear1340";
14 #address-cells = <1>;
15 #size-cells = <1>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>;
47 spdif-in {
51 spdif-out {
59 smi-pmx {
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dxmit.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
17 #include <linux/dma-mapping.h>
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
49 { 104, 216 }, /* 3: 16-QAM 1/2 */
50 { 156, 324 }, /* 4: 16-QAM 3/4 */
51 { 208, 432 }, /* 5: 64-QAM 2/3 */
52 { 234, 486 }, /* 6: 64-QAM 3/4 */
53 { 260, 540 }, /* 7: 64-QAM 5/6 */
64 struct ath_tx_status *ts, int txok);
[all …]
H A Ddynack.c28 * ath_dynack_get_max_to - set max timeout according to channel width
34 const struct ath9k_channel *chan = ah->curchan; in ath_dynack_get_max_to()
49 * ath_dynack_ewma - EWMA (Exponentially Weighted Moving Average) calculation
54 return (new * (EWMA_DIV - EWMA_LEVEL) + in ath_dynack_ewma()
61 * ath_dynack_get_sifs - get sifs time based on phy used
71 if (IS_CHAN_QUARTER_RATE(ah->curchan)) in ath_dynack_get_sifs()
73 else if (IS_CHAN_HALF_RATE(ah->curchan)) in ath_dynack_get_sifs()
82 * ath_dynack_bssidmask - filter out ACK frames based on BSSID mask
92 if ((common->macaddr[i] & common->bssidmask[i]) != in ath_dynack_bssidmask()
93 (mac[i] & common->bssidmask[i])) in ath_dynack_bssidmask()
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsc7280-crd-r3.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include "sc7280-idp.dtsi"
11 #include "sc7280-idp-ec-h1.dtsi"
14 model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)";
15 compatible = "qcom,sc7280-crd",
16 "google,hoglin-rev3", "google,hoglin-rev4",
17 "google,piglin-rev3", "google,piglin-rev4",
25 stdout-path = "serial0:115200n8";
30 regulators-2 {
[all …]
H A Dsc7280-qcard.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
15 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
16 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
17 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
34 wcd9385: audio-codec-1 {
35 compatible = "qcom,wcd9385-codec";
36 pinctrl-names = "default", "sleep";
37 pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>;
38 pinctrl-1 = <&wcd_reset_n_sleep>, <&us_euro_hs_sel>;
[all …]
H A Dmsm8998-fxtec-pro1.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
20 chassis-type = "handset";
21 qcom,board-id = <0x02000b 0x10>;
29 * Until we hook up type-c detection, we
32 extcon_usb: extcon-usb {
33 compatible = "linux,extcon-usb-gpio";
[all …]
H A Dmsm8998-xiaomi-sagit.dts1 // SPDX-License-Identifier: BSD-3-Clause
3 * Xiaomi Mi 6 (sagit) device tree source based on msm8998-mtp.dtsi
10 /dts-v1/;
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/leds/common.h>
18 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
24 /delete-node/ &adsp_mem;
25 /delete-node/ &mpss_mem;
26 /delete-node/ &venus_mem;
27 /delete-node/ &mba_mem;
[all …]
/linux/drivers/net/vmxnet3/
H A Dvmxnet3_defs.h4 * Copyright (C) 2008-2024, VMware, Inc. All Rights Reserved.
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * Maintained by: pv-drivers@vmware.com
55 VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */
62 VMXNET3_REG_LB_TXPROD = 0x1000, /* Tx Producer Index */
73 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
133 * Little Endian layout of bitfields -
139 * Big Endian layout of bitfields -
264 u64 tsi:1; //bit to indicate to set ts
270 struct Vmxnet3TSInfo ts; member
[all …]
/linux/drivers/net/wireless/quantenna/qtnfmac/pcie/
H A Dtopaz_pcie.c1 // SPDX-License-Identifier: GPL-2.0+
103 static void qtnf_deassert_intx(struct qtnf_pcie_topaz_state *ts) in qtnf_deassert_intx() argument
105 void __iomem *reg = ts->base.sysctl_bar + TOPAZ_PCIE_CFG0_OFFSET; in qtnf_deassert_intx()
113 static inline int qtnf_topaz_intx_asserted(struct qtnf_pcie_topaz_state *ts) in qtnf_topaz_intx_asserted() argument
115 void __iomem *reg = ts->base.sysctl_bar + TOPAZ_PCIE_CFG0_OFFSET; in qtnf_topaz_intx_asserted()
121 static void qtnf_topaz_reset_ep(struct qtnf_pcie_topaz_state *ts) in qtnf_topaz_reset_ep() argument
124 TOPAZ_LH_IPC4_INT(ts->base.sysctl_bar)); in qtnf_topaz_reset_ep()
126 pci_restore_state(ts->base.pdev); in qtnf_topaz_reset_ep()
129 static void setup_rx_irqs(struct qtnf_pcie_topaz_state *ts) in setup_rx_irqs() argument
131 void __iomem *reg = PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(ts->base.dmareg_bar); in setup_rx_irqs()
[all …]
/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
30 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
47 * +--------------+ +--------------+
49 * *--------------+ +--------------+
52 * +--------------+ +--------------+
54 * *--------------+ +--------------+
58 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
61 * 2^43 * 10^-9 / 3600 = 2.4 hours
89 * represents units of 2^-32 nanoseconds, and uses 31 bits for this, with the
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9x5ek.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
11 model = "Atmel AT91SAM9X5-EK";
16 stdout-path = "serial0:115200n8";
20 compatible = "atmel,sam9x5-wm8731-audio";
24 atmel,audio-routing =
30 atmel,ssc-controller = <&ssc0>;
31 atmel,audio-codec = <&wm8731>;
36 atmel,adc-ts-wires = <4>;
37 atmel,adc-ts-pressure-threshold = <10000>;
[all …]
/linux/drivers/net/can/spi/mcp251xfd/
H A Dmcp251xfd-tef.c1 // SPDX-License-Identifier: GPL-2.0
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
6 // Marc Kleine-Budde <kernel@pengutronix.de>
36 err = regmap_read(priv->map_reg, MCP251XFD_REG_TEFUA, &tef_ua); in mcp251xfd_tef_tail_get_from_chip()
59 netdev_err(priv->ndev, in mcp251xfd_check_tef_tail()
62 return -EILSEQ; in mcp251xfd_check_tef_tail()
73 struct net_device_stats *stats = &priv->ndev->stats; in mcp251xfd_handle_tefif_one()
81 hw_tef_obj->flags); in mcp251xfd_handle_tefif_one()
82 tef_tail_masked = priv->tef->tail & in mcp251xfd_handle_tefif_one()
86 * bits of a FIFOSTA register, here the TX FIFO tail index in mcp251xfd_handle_tefif_one()
[all …]
/linux/arch/arm/boot/dts/cirrus/
H A Dep93xx-ts7250.dts1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
10 model = "TS-7250 SBC";
11 #address-cells = <1>;
12 #size-cells = <1>;
25 compatible = "gpio-leds";
26 led-0 {
29 linux,default-trigger = "heartbeat";
33 led-1 {
42 nand-controller@60000000 {
[all …]
/linux/drivers/net/ethernet/cadence/
H A Dmacb_ptp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017 Cadence Design Systems - https://www.cadence.com
26 #define GEM_PTP_TIMER_NAME "gem-ptp-timer"
31 if (bp->hw_dma_cap == HW_DMA_CAP_PTP) in macb_ptp_desc()
34 if (bp->hw_dma_cap == HW_DMA_CAP_64B_PTP) in macb_ptp_desc()
41 static int gem_tsu_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts, in gem_tsu_get_time() argument
49 spin_lock_irqsave(&bp->tsu_clk_lock, flags); in gem_tsu_get_time()
59 /* if so, use later read & re-read seconds in gem_tsu_get_time()
63 ts->tv_nsec = gem_readl(bp, TN); in gem_tsu_get_time()
68 ts->tv_nsec = first; in gem_tsu_get_time()
[all …]
/linux/drivers/net/ethernet/google/gve/
H A Dgve_desc_dqo.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2015-2021 Google, Inc.
21 /* Basic TX descriptor (DTYPE 0x0C) */
37 /* The TX completion associated with this packet will contain this tag.
46 #define GVE_TX_MAX_BUF_SIZE_DQO ((16 * 1024) - 1)
48 /* Maximum number of data descriptors allowed per packet, or per-TSO segment. */
54 /* "report_event" on TX packet descriptors may only be reported on the last
55 * descriptor of a TX packet, and they must be spaced apart with at least this
70 /* TX Native TSO Context DTYPE (0x05)
79 /* Max segment size in TSO excluding headers. */
[all …]
/linux/tools/testing/selftests/net/
H A Dtxtimestamp.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Test software tx timestamping, including
8 * - SCHED, SND and ACK timestamps
9 * - RAW, UDP and TCP
10 * - IPv4 and IPv6
11 * - various packet sizes (to test GSO and TSO)
17 * A simple `nc6 [-u] -l -p $DESTPORT` will do
87 static int saved_tskey = -1;
88 static int saved_tskey_type = -1;
92 int64_t max; member
[all …]
/linux/drivers/scsi/hisi_sas/
H A Dhisi_sas_v1_hw.c1 // SPDX-License-Identifier: GPL-2.0-or-later
313 /* dma tx */
340 /* trans tx */
414 void __iomem *regs = hisi_hba->regs + off; in hisi_sas_read32()
422 void __iomem *regs = hisi_hba->regs + off; in hisi_sas_write32()
430 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; in hisi_sas_phy_write32()
438 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; in hisi_sas_phy_read32()
471 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); in config_id_frame_v1_hw()
472 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); in config_id_frame_v1_hw()
493 struct domain_device *device = sas_dev->sas_device; in setup_itct_v1_hw()
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx51-ts4800.dts2 * Copyright 2015 Savoir-faire Linux
4 * This device tree is based on imx51-babbage.dts
9 /dts-v1/;
13 model = "Technologic Systems TS-4800";
14 compatible = "technologic,imx51-ts4800", "fsl,imx51";
17 stdout-path = &uart1;
27 clock-frequency = <22579200>;
31 clock-frequency = <24576000>;
35 backlight_reg: regulator-backlight {
36 compatible = "regulator-fixed";
[all …]

12345