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/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
[all …]
H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 segments of memory for buffering TX and RX, as well as the capability of
14 offloading TX/RX checksum calculation off the processor.
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
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H A Damd-xgbe.txt1 * AMD 10GbE driver (amd-xgbe)
4 - compatible: Should be "amd,xgbe-seattle-v1a"
5 - reg: Address and length of the register sets for the device
6 - MAC registers
7 - PCS registers
8 - SerDes Rx/Tx registers
9 - SerDes integration registers (1/2)
10 - SerDes integration registers (2/2)
11 - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt
13 amd,per-channel-interrupt property is specified, then one additional
[all …]
H A Daltr,tse.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Chevallier <maxime.chevallier@bootlin.com>
15 - const: altr,tse-1.0
16 - const: ALTR,tse-1.0
18 - const: altr,tse-msgdma-1.0
23 interrupt-names:
25 - const: rx_irq
26 - const: tx_irq
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/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-ufs.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
24 #include "phy-qcom-qmp-common.h"
26 #include "phy-qcom-qmp.h"
27 #include "phy-qcom-qmp-pcs-ufs-v2.h"
28 #include "phy-qcom-qmp-pcs-ufs-v3.h"
29 #include "phy-qcom-qmp-pcs-ufs-v4.h"
30 #include "phy-qcom-qmp-pcs-ufs-v5.h"
31 #include "phy-qcom-qmp-pcs-ufs-v6.h"
33 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
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H A Dphy-qcom-qmp-pcie-msm8996.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
22 #include "phy-qcom-qmp-common.h"
24 #include "phy-qcom-qmp.h"
36 /* set of registers with offsets different per-PHY */
43 /* PCS registers */
139 /* struct qmp_phy_cfg - per-PHY initialization config */
144 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
169 * struct qmp_phy - per-lane phy descriptor
174 * @tx: iomapped memory space for lane's tx
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H A Dphy-qcom-qmp-pcie.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
25 #include <dt-bindings/phy/phy-qcom-qmp.h>
27 #include "phy-qcom-qmp-common.h"
29 #include "phy-qcom-qmp.h"
30 #include "phy-qcom-qmp-pcs-misc-v3.h"
31 #include "phy-qcom-qmp-pcs-pcie-v4.h"
32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
33 #include "phy-qcom-qmp-pcs-pcie-v5.h"
34 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
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H A Dphy-qcom-qmp-usb-legacy.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-misc-v3.h"
25 #include "phy-qcom-qmp-pcs-usb-v4.h"
26 #include "phy-qcom-qmp-pcs-usb-v5.h"
28 #include "phy-qcom-qmp-dp-com-v3.h"
70 /* set of registers with offsets different per-PHY */
72 /* PCS registers */
483 u16 pcs; member
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H A Dphy-qcom-qmp-usb.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
22 #include "phy-qcom-qmp-common.h"
24 #include "phy-qcom-qmp.h"
25 #include "phy-qcom-qmp-pcs-misc-v3.h"
26 #include "phy-qcom-qmp-pcs-misc-v4.h"
27 #include "phy-qcom-qmp-pcs-usb-v4.h"
28 #include "phy-qcom-qmp-pcs-usb-v5.h"
29 #include "phy-qcom-qmp-pcs-usb-v6.h"
30 #include "phy-qcom-qmp-pcs-usb-v7.h"
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/linux/arch/arm64/boot/dts/freescale/
H A Dtqmls1088a-mbls10xxa-mc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
10 #include <dt-bindings/net/ti-dp83867.h>
17 pcs-handle = <&pcs1>;
21 pcs-handle = <&pcs2>;
25 pcs-handle = <&pcs3_0>;
29 pcs-handle = <&pcs3_1>;
33 pcs-handle = <&pcs3_2>;
37 pcs-handle = <&pcs3_3>;
[all …]
H A Dfsl-ls1088a-ten64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
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H A Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
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/linux/drivers/net/ethernet/sun/
H A Dsungem.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 #define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
45 #define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */
46 #define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */
47 #define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */
51 #define GREG_STAT_PCS 0x00002000 /* PCS signalled interrupt */
52 #define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
96 * This register is used to perform a global reset of the RX and TX portions
[all …]
H A Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
70 TX FIFO */
72 TX FIFO. i.e.,
73 TX Kick == TX complete. if
[all …]
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_mdio.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/pcs/pcs-xpcs.h>
12 struct sja1105_mdio_private *mdio_priv = bus->priv; in sja1105_pcs_mdio_read_c45()
13 struct sja1105_private *priv = mdio_priv->priv; in sja1105_pcs_mdio_read_c45()
38 struct sja1105_mdio_private *mdio_priv = bus->priv; in sja1105_pcs_mdio_write_c45()
39 struct sja1105_private *priv = mdio_priv->priv; in sja1105_pcs_mdio_write_c45()
47 return -EINVAL; in sja1105_pcs_mdio_write_c45()
54 struct sja1105_mdio_private *mdio_priv = bus->priv; in sja1110_pcs_mdio_read_c45()
55 struct sja1105_private *priv = mdio_priv->priv; in sja1110_pcs_mdio_read_c45()
56 const struct sja1105_regs *regs = priv->info->regs; in sja1110_pcs_mdio_read_c45()
[all …]
/linux/drivers/net/pcs/
H A Dpcs-xpcs.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/pcs/pcs-xpcs.h>
82 #define DW_VR_MII_EEE_LTX_EN BIT(0) /* LPI Tx Enable */
84 #define DW_VR_MII_EEE_TX_QUIET_EN BIT(2) /* Tx Quiet Enable */
86 #define DW_VR_MII_EEE_TX_EN_CTRL BIT(4) /* Tx Control Enable */
98 static const struct dw_xpcs_info _name = { .pcs = _pcs, .pma = _pma }
113 struct phylink_pcs pcs; member
/linux/drivers/net/ethernet/freescale/fman/
H A Dfman_memac.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
14 #include <linux/pcs-lynx.h>
25 #define CMD_CFG_TX_LOWP_ENA 0x00800000 /* 08 Tx Low Power Idle Enable */
29 #define CMD_CFG_TX_PAD_EN 0x00000800 /* 20 Enable Tx padding of frames */
56 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */
57 #define IF_MODE_10G 0x00000000 /* 30-31 10G interface */
58 #define IF_MODE_MII 0x00000001 /* 30-31 MII interface */
59 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */
62 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */
[all …]
H A Dfman_dtsec.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
29 #define TBICON_AN_SENSE 0x0100 /* Auto-negotiation sense enable */
165 u32 tmr_ctrl; /* 0x020 Time-stamp Control register */
166 u32 tmr_pevent; /* 0x024 Time-stamp event register */
173 u32 igaddr[8]; /* 0x080-0x09C Individual/group address */
174 u32 gaddr[8]; /* 0x0A0-0x0BC Group address registers 0-7 */
179 u32 hafdup; /* 0x10C Half-duplex */
186 u32 exact_match1; /* octets 1-4 */
187 u32 exact_match2; /* octets 5-6 */
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8mq-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Jun <jun.li@nxp.com>
15 - enum:
16 - fsl,imx8mq-usb-phy
17 - fsl,imx8mp-usb-phy
18 - items:
19 - const: fsl,imx95-usb-phy
[all …]
/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
35 /* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
38 /* VLAN Rx & Tx frame support. Default: disabled (cleared) */
109 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
110 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
124 /* Default TX/RX Threshold and delay timer values for SGDMA mode */
129 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
130 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
147 #define XAE_TPF_OFFSET 0x00000004 /* Tx Pause Frame */
[all …]
/linux/drivers/net/ethernet/dlink/
H A Ddl2k.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
4 Copyright (c) 2001, 2002 by D-Link Corporation
6 Created 03-May-2001, base on Linux' sundance.c.
36 #define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used.*/
42 Unlike software-only systems, device drivers interact with complex hardware.
261 /* PCS register */
309 /* Physical Coding Sublayer Management (PCS) */
310 /* PCS control and status registers bitmap as the same as MII */
311 /* PCS Extended Status register bitmap as the same as MII */
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
12 "rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac"
66 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_suspend()
68 return reset_control_assert(mgbe->rst_mac); in tegra_mgbe_suspend()
77 err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_resume()
81 err = reset_control_deassert(mgbe->rst_mac); in tegra_mgbe_resume()
86 writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE); in tegra_mgbe_resume()
89 writel(mgbe->iommu_sid, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL); in tegra_mgbe_resume()
91 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS); in tegra_mgbe_resume()
93 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); in tegra_mgbe_resume()
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr9a06g032.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
30 compatible = "arm,cortex-a7";
33 enable-method = "renesas,r9a06g032-smp";
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman3-0-10g-1-best-effort.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x9>;
38 compatible = "fsl,fman-v3-port-rx";
40 fsl,fman-10g-port;
41 fsl,fman-best-effort-port;
45 cell-index = <0x29>;
46 compatible = "fsl,fman-v3-port-tx";
48 fsl,fman-10g-port;
49 fsl,fman-best-effort-port;
53 cell-index = <1>;
[all …]
H A Dqoriq-fman3-1-10g-0.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x10>;
38 compatible = "fsl,fman-v3-port-rx";
40 fsl,fman-10g-port;
44 cell-index = <0x30>;
45 compatible = "fsl,fman-v3-port-tx";
47 fsl,fman-10g-port;
51 cell-index = <0x8>;
52 compatible = "fsl,fman-memac";
54 fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
[all …]

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