1 // SPDX-License-Identifier: GPL-2.0-only
12 	"rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac"
66 	clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);  in tegra_mgbe_suspend()
68 	return reset_control_assert(mgbe->rst_mac);  in tegra_mgbe_suspend()
77 	err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks);  in tegra_mgbe_resume()
81 	err = reset_control_deassert(mgbe->rst_mac);  in tegra_mgbe_resume()
86 	writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE);  in tegra_mgbe_resume()
89 	writel(mgbe->iommu_sid, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL);  in tegra_mgbe_resume()
91 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS);  in tegra_mgbe_resume()
93 		value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);  in tegra_mgbe_resume()
95 		writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);  in tegra_mgbe_resume()
98 	err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value,  in tegra_mgbe_resume()
102 		dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n");  in tegra_mgbe_resume()
103 		clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);  in tegra_mgbe_resume()
109 		clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);  in tegra_mgbe_resume()
120 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
122 	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
124 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
126 	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
128 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
130 	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
133 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
135 	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
138 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
140 	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
142 	err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL, value,  in mgbe_uphy_lane_bringup_serdes_up()
146 		dev_err(mgbe->dev, "timeout waiting for RX calibration to become enabled\n");  in mgbe_uphy_lane_bringup_serdes_up()
151 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
153 	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
155 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
157 	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
160 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
162 	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
165 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
167 	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
170 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
172 	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_up()
174 	err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_IRQ_STATUS, value,  in mgbe_uphy_lane_bringup_serdes_up()
178 		dev_err(mgbe->dev, "timeout waiting for link to become ready\n");  in mgbe_uphy_lane_bringup_serdes_up()
183 	writel(value, mgbe->xpcs + XPCS_WRAP_IRQ_STATUS);  in mgbe_uphy_lane_bringup_serdes_up()
193 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_down()
195 	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_down()
197 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_down()
199 	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_down()
201 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_down()
203 	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_down()
205 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_down()
207 	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_down()
209 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_down()
211 	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);  in mgbe_uphy_lane_bringup_serdes_down()
222 	mgbe = devm_kzalloc(&pdev->dev, sizeof(*mgbe), GFP_KERNEL);  in tegra_mgbe_probe()
224 		return -ENOMEM;  in tegra_mgbe_probe()
226 	mgbe->dev = &pdev->dev;  in tegra_mgbe_probe()
234 	mgbe->hv = devm_platform_ioremap_resource_byname(pdev, "hypervisor");  in tegra_mgbe_probe()
235 	if (IS_ERR(mgbe->hv))  in tegra_mgbe_probe()
236 		return PTR_ERR(mgbe->hv);  in tegra_mgbe_probe()
238 	mgbe->regs = devm_platform_ioremap_resource_byname(pdev, "mac");  in tegra_mgbe_probe()
239 	if (IS_ERR(mgbe->regs))  in tegra_mgbe_probe()
240 		return PTR_ERR(mgbe->regs);  in tegra_mgbe_probe()
242 	mgbe->xpcs = devm_platform_ioremap_resource_byname(pdev, "xpcs");  in tegra_mgbe_probe()
243 	if (IS_ERR(mgbe->xpcs))  in tegra_mgbe_probe()
244 		return PTR_ERR(mgbe->xpcs);  in tegra_mgbe_probe()
247 	if (!tegra_dev_iommu_get_stream_id(mgbe->dev, &mgbe->iommu_sid)) {  in tegra_mgbe_probe()
248 		dev_err(mgbe->dev, "failed to get iommu stream id\n");  in tegra_mgbe_probe()
249 		return -EINVAL;  in tegra_mgbe_probe()
252 	res.addr = mgbe->regs;  in tegra_mgbe_probe()
255 	mgbe->clks = devm_kcalloc(&pdev->dev, ARRAY_SIZE(mgbe_clks),  in tegra_mgbe_probe()
256 				  sizeof(*mgbe->clks), GFP_KERNEL);  in tegra_mgbe_probe()
257 	if (!mgbe->clks)  in tegra_mgbe_probe()
258 		return -ENOMEM;  in tegra_mgbe_probe()
261 		mgbe->clks[i].id = mgbe_clks[i];  in tegra_mgbe_probe()
263 	err = devm_clk_bulk_get(mgbe->dev, ARRAY_SIZE(mgbe_clks), mgbe->clks);  in tegra_mgbe_probe()
267 	err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks);  in tegra_mgbe_probe()
272 	mgbe->rst_mac = devm_reset_control_get(&pdev->dev, "mac");  in tegra_mgbe_probe()
273 	if (IS_ERR(mgbe->rst_mac)) {  in tegra_mgbe_probe()
274 		err = PTR_ERR(mgbe->rst_mac);  in tegra_mgbe_probe()
278 	err = reset_control_assert(mgbe->rst_mac);  in tegra_mgbe_probe()
284 	err = reset_control_deassert(mgbe->rst_mac);  in tegra_mgbe_probe()
288 	/* Perform PCS reset */  in tegra_mgbe_probe()
289 	mgbe->rst_pcs = devm_reset_control_get(&pdev->dev, "pcs");  in tegra_mgbe_probe()
290 	if (IS_ERR(mgbe->rst_pcs)) {  in tegra_mgbe_probe()
291 		err = PTR_ERR(mgbe->rst_pcs);  in tegra_mgbe_probe()
295 	err = reset_control_assert(mgbe->rst_pcs);  in tegra_mgbe_probe()
301 	err = reset_control_deassert(mgbe->rst_pcs);  in tegra_mgbe_probe()
311 	plat->has_xgmac = 1;  in tegra_mgbe_probe()
312 	plat->flags |= STMMAC_FLAG_TSO_EN;  in tegra_mgbe_probe()
313 	plat->pmt = 1;  in tegra_mgbe_probe()
314 	plat->bsp_priv = mgbe;  in tegra_mgbe_probe()
316 	if (!plat->mdio_node)  in tegra_mgbe_probe()
317 		plat->mdio_node = of_get_child_by_name(pdev->dev.of_node, "mdio");  in tegra_mgbe_probe()
319 	if (!plat->mdio_bus_data) {  in tegra_mgbe_probe()
320 		plat->mdio_bus_data = devm_kzalloc(&pdev->dev, sizeof(*plat->mdio_bus_data),  in tegra_mgbe_probe()
322 		if (!plat->mdio_bus_data) {  in tegra_mgbe_probe()
323 			err = -ENOMEM;  in tegra_mgbe_probe()
328 	plat->mdio_bus_data->needs_reset = true;  in tegra_mgbe_probe()
330 	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS);  in tegra_mgbe_probe()
332 		value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);  in tegra_mgbe_probe()
334 		writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);  in tegra_mgbe_probe()
337 	err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value,  in tegra_mgbe_probe()
341 		dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n");  in tegra_mgbe_probe()
345 	plat->serdes_powerup = mgbe_uphy_lane_bringup_serdes_up;  in tegra_mgbe_probe()
346 	plat->serdes_powerdown = mgbe_uphy_lane_bringup_serdes_down;  in tegra_mgbe_probe()
348 	/* Tx FIFO Size - 128KB */  in tegra_mgbe_probe()
349 	plat->tx_fifo_size = 131072;  in tegra_mgbe_probe()
350 	/* Rx FIFO Size - 192KB */  in tegra_mgbe_probe()
351 	plat->rx_fifo_size = 196608;  in tegra_mgbe_probe()
354 	writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE);  in tegra_mgbe_probe()
357 	writel(mgbe->iommu_sid, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL);  in tegra_mgbe_probe()
359 	plat->flags |= STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP;  in tegra_mgbe_probe()
361 	err = stmmac_dvr_probe(&pdev->dev, plat, &res);  in tegra_mgbe_probe()
368 	clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);  in tegra_mgbe_probe()
375 	struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(&pdev->dev);  in tegra_mgbe_remove()
377 	clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);  in tegra_mgbe_remove()
383 	{ .compatible = "nvidia,tegra234-mgbe", },
394 		.name = "tegra-mgbe",