Lines Matching +full:tx +full:- +full:pcs
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 segments of memory for buffering TX and RX, as well as the capability of
14 offloading TX/RX checksum calculation off the processor.
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
35 axistream-connected is specified, in which case the reg
42 - description: Ethernet core interrupt
43 - description: Tx DMA interrupt
44 - description: Rx DMA interrupt
46 Ethernet core interrupt is optional. If axistream-connected property is
47 present DMA node should contains TX/RX DMA interrupts else DMA interrupt
51 phy-handle: true
55 Set to allocated memory buffer for Rx/Tx in the hardware.
58 phy-mode:
60 - mii
61 - gmii
62 - rgmii
63 - sgmii
64 - 1000base-x
66 xlnx,phy-type:
68 Do not use, but still accepted in preference to phy-mode.
74 TX checksum offload. 0 or empty for disabling TX checksum offload,
75 1 to enable partial TX checksum offload and 2 to enable full TX
88 xlnx,switch-x-sgmii:
92 SGMII modes. If set, the phy-mode should be set to match the mode
97 - description: Clock for AXI register slave interface.
98 - description: AXI4-Stream clock for TXD RXD TXC and RXS interfaces.
99 - description: Ethernet reference clock, used by signal delay primitives
101 - description: MGT reference clock (used by optional internal PCS/PMA PHY)
103 clock-names:
105 - const: s_axi_lite_clk
106 - const: axis_clk
107 - const: ref_clk
108 - const: mgt_clk
110 axistream-connected:
113 used by this device. If this is specified, the DMA-related resources
114 from that device (DMA registers and DMA TX/RX interrupts) rather than
120 pcs-handle:
121 description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
122 modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
123 and "phy-handle" should point to an external PHY if exists.
129 description: TX and RX DMA channel phandle
131 dma-names:
133 pattern: "^[tr]x_chan([0-9]|1[0-5])$"
135 Should be "tx_chan0", "tx_chan1" ... "tx_chan15" for DMA Tx channel
141 - compatible
142 - interrupts
143 - reg
144 - xlnx,rxmem
145 - phy-handle
148 - $ref: /schemas/net/ethernet-controller.yaml#
153 - |
155 compatible = "xlnx,axi-ethernet-1.00.a";
157 clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
159 phy-mode = "mii";
162 dma-names = "tx_chan0", "rx_chan0";
166 phy-handle = <&phy0>;
169 #address-cells = <1>;
170 #size-cells = <0>;
171 phy0: ethernet-phy@1 {
172 device_type = "ethernet-phy";
178 - |
180 compatible = "xlnx,axi-ethernet-1.00.a";
182 clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
184 phy-mode = "mii";
189 phy-handle = <&phy1>;
190 axistream-connected = <&dma>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 phy1: ethernet-phy@1 {
196 device_type = "ethernet-phy";