| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | ti,dp83869.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
22 SGMII The DP83869HM supports Media Conversion in Managed mode. In this mode,
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| H A D | motorcomm,yt8xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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| H A D | adi,adin.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
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| H A D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
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| H A D | qcom,qca807x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Robert Marko <robert.marko@sartura.hr>
15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
21 Both models have a combo port that supports 1000BASE-X and
22 100BASE-FX fiber.
25 output only pins that natively drive LED-s for up to 2 attached
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| H A D | sff,sfp.txt | 1 Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
6 - compatible : must be one of
10 - i2c-bus : phandle of an I2C bus controller for the SFP two wire serial
15 - mod-def0-gpios : GPIO phandle and a specifier of the MOD-DEF0 (AKA Mod_ABS)
19 - los-gpios : GPIO phandle and a specifier of the Receiver Loss of Signal
22 - tx-fault-gpios : GPIO phandle and a specifier of the Module Transmitter
25 - tx-disable-gpios : GPIO phandle and a specifier of the Transmitter Disable
26 output gpio signal, active (Tx disable) high
28 - rate-select0-gpios : GPIO phandle and a specifier of the Rx Signaling Rate
29 Select (AKA RS0) output gpio signal, low: low Rx rate, high: high Rx rate
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| H A D | sff,sfp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
11 - Russell King <linux@armlinux.org.uk>
16 - sff,sfp # for SFP modules
17 - sff,sff # for soldered down SFF modules
19 i2c-bus:
24 maximum-power-milliwatt:
29 allowable by a module in the slot, in milli-Watts. Presently, modules can
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| /freebsd/sys/contrib/device-tree/Bindings/net/can/ |
| H A D | sja1000.txt | 5 - compatible : should be one of "nxp,sja1000", "technologic,sja1000".
7 - reg : should specify the chip select, address offset and size required
10 - interrupts: property with a value describing the interrupt source
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
20 - nxp,external-clock-frequency : Frequency of the external oscillator
25 - nxp,tx-output-mode : operation mode of the TX output control logic:
26 <0x0> : bi-phase output mode
27 <0x1> : normal output mode (default)
28 <0x2> : test output mode
29 <0x3> : clock output mode
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| H A D | nxp,sja1000.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
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| /freebsd/sys/contrib/device-tree/src/arm64/microchip/ |
| H A D | sparx5_pcb134_board.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
16 i2c0_imux: i2c-mux-0 {
17 compatible = "i2c-mux-pinctrl";
18 #address-cells = <1>;
19 #size-cells = <0>;
20 i2c-parent = <&i2c0>;
23 i2c0_emux: i2c-mux-1 {
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| H A D | sparx5_pcb135_board.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
16 i2c0_imux: i2c-mux {
17 compatible = "i2c-mux-pinctrl";
18 #address-cells = <1>;
19 #size-cells = <0>;
20 i2c-parent = <&i2c0>;
24 compatible = "gpio-leds";
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| /freebsd/sys/contrib/alpine-hal/eth/ |
| H A D | al_hal_eth.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
61 /* *INDENT-OFF* */
65 /* *INDENT-ON* */
97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200)
130 /** MAC media mode */
137 AL_ETH_MAC_MODE_XLG_LL_40G, /**< applies to 40G mode using the 40G low latency (LL) MAC */
138 AL_ETH_MAC_MODE_KR_LL_25G, /**< applies to 25G mode using the 10/25G low latency (LL) MAC */
139 AL_ETH_MAC_MODE_XLG_LL_50G, /**< applies to 50G mode using the 40/50G low latency (LL) MAC */
140 AL_ETH_MAC_MODE_XLG_LL_25G /**< applies to 25G mode using the 40/50G low latency (LL) MAC */
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| H A D | al_hal_eth_mac_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
309 struct al_eth_mac_10g_stats_v3_tx tx; member
428 /* [0x5c] SerDes TX FIFO control */
430 /* [0x60] SerDes TX FIFO status */
482 /* [0x4] EEE, number of times the MAC went into low power mode */
484 /* [0x8] EEE, number of times the MAC went out of low power mode */
550 /* [0x4] TX ASYNC FIFO configuration */
552 /* [0x8] TX ASYNC FIFO configuration */
554 /* [0xc] TX ASYNC FIFO configuration */
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | fsl-sai.txt | 10 - compatible : Compatible list, contains "fsl,vf610-sai",
11 "fsl,imx6sx-sai", "fsl,imx6ul-sai",
12 "fsl,imx7ulp-sai", "fsl,imx8mq-sai",
13 "fsl,imx8qm-sai", "fsl,imx8mm-sai",
14 "fsl,imx8mn-sai", "fsl,imx8mp-sai", or
15 "fsl,imx8ulp-sai".
17 - reg : Offset and length of the register set for the device.
19 - clocks : Must contain an entry for each entry in clock-names.
21 - clock-names : Must include the "bus" for register access and
27 - dmas : Generic dma devicetree binding as described in
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| H A D | fsl,sai.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
21 - items:
22 - enum:
23 - fsl,imx6ul-sai
24 - fsl,imx7d-sai
25 - const: fsl,imx6sx-sai
27 - items:
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| /freebsd/sys/contrib/device-tree/Bindings/serial/ |
| H A D | fsl-imx-uart.txt | 4 - compatible : Should be "fsl,<soc>-uart"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain uart interrupt
9 - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
10 in DCE mode by default.
11 - fsl,inverted-tx , fsl,inverted-rx : Indicate that the hardware attached
13 respectively, and that the peripheral should invert its output/input
15 - rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,
16 linux,rs485-enabled-at-boot-time: see rs485.txt. Note that for RS485
17 you must enable either the "uart-has-rtscts" or the "rts-gpios"
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| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | sm8550-hdk.dts | 1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
22 compatible = "qcom,sm8550-hdk", "qcom,sm8550";
23 chassis-type = "embedded";
30 wcd938x: audio-codec {
31 compatible = "qcom,wcd9385-codec";
33 pinctrl-names = "default";
34 pinctrl-0 = <&wcd_default>;
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| H A D | sa8775p-ride.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include "sa8775p-pmics.dtsi"
28 stdout-path = "serial0:115200n8";
33 regulators-0 {
34 compatible = "qcom,pmm8654au-rpmh-regulators";
35 qcom,pmic-id = "a";
38 regulator-name = "vreg_s4a";
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| H A D | sm8550-mtp.dts | 1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
22 compatible = "qcom,sm8550-mtp", "qcom,sm8550";
23 chassis-type = "handset";
29 wcd938x: audio-codec {
30 compatible = "qcom,wcd9385-codec";
32 pinctrl-names = "default";
33 pinctrl-0 = <&wcd_default>;
35 qcom,micbias1-microvolt = <1800000>;
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| H A D | sm8650-hdk.dts | 1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
21 compatible = "qcom,sm8650-hdk", "qcom,sm8650";
22 chassis-type = "embedded";
30 stdout-path = "serial0:115200n8";
33 hdmi-out {
34 compatible = "hdmi-connector";
39 remote-endpoint = <<9611_out>;
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| /freebsd/sys/dev/mii/ |
| H A D | nsphyreg.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
50 #define MII_NSPHY_PCR 0x17 /* PCS sub-layer configuration */
51 #define PCR_NRZI 0x8000 /* NRZI encoding enabled for 100TX */
54 #define PCR_REPEATER 0x1000 /* repeater mode */
55 #define PCR_ENCSEL 0x0800 /* encoder mode select */
60 #define PCR_LED1MODE 0x0004 /* LED1 mode: see below */
61 #define PCR_LED4MODE 0x0002 /* LED4 mode: see below */
64 * LED1 Mode:
66 * 1 LED1 output configured to PAR's CON_STATUS, useful for
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| /freebsd/sys/dev/smc/ |
| H A D | if_smcreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
40 #define TCR_LOOP 0x0002 /* Put the PHY into loopback mode */
42 #define TCR_PAD_EN 0x0080 /* Pad TX frames to 64 bytes */
46 #define TCR_STP_SQET 0x1000 /* Stop TX on signal quality error */
52 #define EPHSR_TX_SUC 0x0001 /* Last TX was successful */
53 #define EPHSR_SNGLCOL 0x0002 /* Single collision on last TX */
54 #define EPHSR_MULCOL 0x0004 /* Multiple collisions on last TX */
55 #define EPHSR_LTX_MULT 0x0008 /* Last TX was multicast */
56 #define EPHSR_16COL 0x0010 /* 16 collisions on last TX */
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | dwc3.txt | 3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
20 "samsung,exynos5250-dwusb3"
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| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_freebsd_inc.h | 12 #define AH_NEED_TX_DATA_SWAP 0 /* TX descriptor swap? */
13 #define AH_NEED_RX_DATA_SWAP 0 /* TX descriptor swap? */
59 #define OS_ATOMIC_DEC(a) (*a)--
84 * Green Tx, Based on different RSSI of Received Beacon thresholds,
85 * using different tx power by modified register tx power related values.
105 matched filter (single-sided) in usecs */
106 u_int32_t rp_threshold; /* Threshold for MF output to indicate
114 int32_t rp_rssimargin; /* rssi threshold margin. In Turbo Mode HW reports rssi 3dBm */
115 /* lower than in non TURBO mode.
128 matched filter (single-sided) in usecs */
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| /freebsd/sys/dev/igc/ |
| H A D | igc_defines.h | 1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
64 #define IGC_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
149 #define IGC_RCTL_LBM_NO 0x00000000 /* no loopback mode */
150 #define IGC_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
151 #define IGC_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
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