Lines Matching +full:tx +full:- +full:output +full:- +full:mode
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
64 #define IGC_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
149 #define IGC_RCTL_LBM_NO 0x00000000 /* no loopback mode */
150 #define IGC_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
151 #define IGC_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
214 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
216 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
228 #define IGC_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
233 #define IGC_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
278 /* 1000/H is not supported, nor spec-compliant. */
324 #define IGC_TCTL_EN 0x00000002 /* enable Tx */
328 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
332 #define IGC_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
345 /* GPY211 - I225 defines */
474 #define IGC_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
475 #define IGC_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
476 #define IGC_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
477 #define IGC_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
502 #define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */
506 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
524 #define IGC_EIMS_TX_QUEUE0 IGC_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
525 #define IGC_EIMS_TX_QUEUE1 IGC_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
526 #define IGC_EIMS_TX_QUEUE2 IGC_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
527 #define IGC_EIMS_TX_QUEUE3 IGC_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
541 #define IGC_EICS_TX_QUEUE0 IGC_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
542 #define IGC_EICS_TX_QUEUE1 IGC_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
543 #define IGC_EICS_TX_QUEUE2 IGC_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
544 #define IGC_EICS_TX_QUEUE3 IGC_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
604 /* Loop limit on how long we wait for auto-negotiation to complete */
626 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
634 #define IGC_TSYNCTXCTL_TXTT_0 0x00000001 /* Tx timestamp reg 0 valid */
635 #define IGC_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
705 #define TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0. */
706 #define TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */
707 #define TS_SDP1_SEL_TT0 (0u << 9) /* Target time 0 is output on SDP1. */
708 #define TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1. */
709 #define TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */
710 #define TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */
711 #define TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */
712 #define TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */
713 #define TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2. */
714 #define TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */
715 #define TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */
716 #define TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */
717 #define TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3. */
718 #define TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */
719 #define TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */
720 #define TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */
771 #define IGC_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */
786 #define IGC_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
792 #define IGC_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */
852 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
853 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
864 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */
865 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */
877 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */
878 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */
880 /* 1000BASE-T Control Register */
896 /* 1000BASE-T Status Register */
903 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */
917 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
919 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
920 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1030 /* NVM Commands - Microwire */
1037 /* NVM Commands - SPI */
1041 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1069 /* PCI/PCI-X/PCI-EX Config space */
1095 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1125 /* MDI Crossover Mode bits 6:5 Manual MDI configuration */
1128 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1132 #define M88IGC_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
1139 * 1 = 50-80M
1140 * 2 = 80-110M
1141 * 3 = 110-140M
1170 * 15-5: page
1171 * 4-0: register offset
1189 /* Page 193 - Port Control Registers */
1190 /* Kumeran Mode Control */
1194 /* Page 194 - KMRN Registers */
1208 #define IGC_N0_QUEUE -1
1230 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1254 #define IGC_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */
1259 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1260 * of EEE LPI Tx state
1263 /* Minimum time for 100BASE-T where no data will be transmit following move out
1264 * of EEE LPI Tx state
1288 #define IGC_TXPB0S_SIZE_I225_MASK 0x0000003F /* Tx packet buffer 0 size */