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/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_config.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 /* Tx instruction types by length */
15 /* Tx Queue: maximum descriptors per ring */
17 /* Minimum input (Tx) requests to be enqueued to ring doorbell */
19 /* Packet threshold for Tx queue interrupt */
42 /* Tx Queue wake threshold
43 * wakeup a stopped Tx queue if minimum 2 descriptors are available.
44 * Even a skb with fragments consume only one Tx queue descriptor entry.
51 #define OCTEP_VF_MAX_MTU (10000 - (ETH_HLEN + ETH_FCS_LEN))
55 /* Macros to get octeon config params */
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/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_config.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 /* Tx instruction types by length */
15 /* Tx Queue: maximum descriptors per ring */
18 /* Minimum input (Tx) requests to be enqueued to ring doorbell */
20 /* Packet threshold for Tx queue interrupt */
43 /* Tx Queue wake threshold
44 * wakeup a stopped Tx queue if minimum 2 descriptors are available.
45 * Even a skb with fragments consume only one Tx queue descriptor entry.
59 /* Macros to get octeon config params */
60 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
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/linux/Documentation/devicetree/bindings/net/can/
H A Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - const: renesas,r9a06g032-sja1000 # RZ/N1D
20 - const: renesas,rzn1-sja1000 # RZ/N1
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/linux/net/mac80211/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 config MAC80211
21 config MAC80211_HAS_RC
24 config MAC80211_RC_MINSTREL
29 This option enables the 'minstrel' TX rate control algorithm
41 config MAC80211_RC_DEFAULT_MINSTREL
50 config MAC80211_RC_DEFAULT
60 config MAC80211_KUNIT_TEST
70 config MAC80211_MESH
76 over (possibly multi-hop) wireless links to form a single logical
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/linux/Documentation/devicetree/bindings/sound/
H A Dti,tlv320adcx140.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Andrew Davis <afd@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
28 - ti,tlv320adc3140
29 - ti,tlv320adc5140
30 - ti,tlv320adc6140
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/linux/sound/soc/meson/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
5 config SND_MESON_AIU
12 Select Y or M to add support for the Audio output subsystem found
15 config SND_MESON_AXG_FIFO
21 config SND_MESON_AXG_FRDDR
28 config SND_MESON_AXG_TODDR
35 config SND_MESON_AXG_TDM_FORMATTER
40 config SND_MESON_AXG_TDM_INTERFACE
44 config SND_MESON_AXG_TDMIN
52 config SND_MESON_AXG_TDMOUT
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/linux/drivers/media/i2c/adv748x/
H A Dadv748x-csi2.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Analog Devices ADV748X CSI-2 Transmitter
10 #include <media/v4l2-ctrls.h>
11 #include <media/v4l2-device.h>
12 #include <media/v4l2-ioctl.h>
25 int adv748x_csi2_set_virtual_channel(struct adv748x_csi2 *tx, unsigned int vc) in adv748x_csi2_set_virtual_channel() argument
27 return tx_write(tx, ADV748X_CSI_VC_REF, vc << ADV748X_CSI_VC_REF_SHIFT); in adv748x_csi2_set_virtual_channel()
33 * @tx: CSI2 private entity
36 * @src_pad: Pad number of source to link to this @tx
42 static int adv748x_csi2_register_link(struct adv748x_csi2 *tx, in adv748x_csi2_register_link() argument
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/linux/drivers/platform/mellanox/
H A Dmlxbf-tmfifo.c1 // SPDX-License-Identifier: GPL-2.0+
24 #include "mlxbf-tmfifo-regs.h"
29 /* Console Tx buffer size. */
32 /* Console Tx buffer reserved space. */
35 /* House-keeping timer interval. */
50 /* Tx timeout in milliseconds. */
53 /* ACPI UID for BlueField-3. */
59 * struct mlxbf_tmfifo_vring - Structure of the TmFifo virtual ring
75 * @tx_timeout: expire time of last tx packet
101 r->desc_head == &r->drop_desc; })
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/linux/drivers/net/ethernet/smsc/
H A Dsmc91x.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*------------------------------------------------------------------------
3 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
21 ---------------------------------------------------------------------------*/
29 * Any 16-bit access is performed with two 8-bit accesses if the hardware
30 * can't do it directly. Most registers are 16-bit so those are mandatory.
55 #include <asm/mach-types.h>
65 #define SMC_IO_SHIFT (lp->io_shift)
96 #define SMC_IRQ_FLAGS (-1) /* from resource */
114 (lp)->cfg.pxa_u16_align4)
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* The ice hardware captures Tx hardware timestamps in the PHY. The timestamp
18 * re-use of an index for multiple packets.
21 * that an index is not re-used for multiple transmitted packets. The
22 * structures and functions declared in this file track the available Tx
29 * The timestamp blocks are handled differently for E810- and E822-based
35 * +--------+--------+--------+--------+--------+--------+--------+--------+
40 * +--------+--------+--------+--------+--------+--------+--------+--------+
43 * |--- quad offset is always 0
44 * ---- quad number
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H A Dice_common.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2023, Intel Corporation. */
90 * ice_dump_phy_type - helper function to dump phy_type
117 * ice_set_mac_type - Sets MAC type
125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) in ice_set_mac_type()
126 return -ENODEV; in ice_set_mac_type()
128 switch (hw->device_id) { in ice_set_mac_type()
135 hw->mac_type = ICE_MAC_E810; in ice_set_mac_type()
156 hw->mac_type = ICE_MAC_GENERIC; in ice_set_mac_type()
162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; in ice_set_mac_type()
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/linux/sound/soc/atmel/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
5 config SND_ATMEL_SOC_PDC
8 config SND_ATMEL_SOC_DMA
12 config SND_ATMEL_SOC_SSC
17 config SND_ATMEL_SOC_SSC_PDC
24 in PDC mode configured using audio-graph-card in device-tree.
26 config SND_ATMEL_SOC_SSC_DMA
33 in DMA mode configured using audio-graph-card in device-tree.
35 config SND_AT91_SOC_SAM9G20_WM8731
36 tristate "SoC Audio support for WM8731-based At91sam9g20 evaluation board"
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/linux/drivers/net/ethernet/qlogic/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 config NET_VENDOR_QLOGIC
20 config QLA3XXX
29 config QLCNIC
37 config QLCNIC_SRIOV
38 bool "QLOGIC QLCNIC 83XX family SR-IOV Support"
42 This configuration parameter enables Single Root Input Output
47 config QLCNIC_DCB
56 to Tx.
58 config QLCNIC_HWMON
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/linux/Documentation/networking/device_drivers/ethernet/aquantia/
H A Datlantic.rst1 .. SPDX-License-Identifier: GPL-2.0
8 For the aQuantia Multi-Gigabit PCI Express Family of Ethernet Adapters
12 - Identifying Your Adapter
13 - Configuration
14 - Supported ethtool options
15 - Command Line Parameters
16 - Config file parameters
17 - Support
18 - License
23 The driver in this release is compatible with AQC-100, AQC-107, AQC-108
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/linux/drivers/clk/st/
H A Dclk-flexgen.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-flexgen.c
5 * Copyright (C) ST-Microelectronics SA 2013
6 * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
10 #include <linux/clk-provider.h>
36 /* Pre-divisor's gate */
38 /* Pre-divisor */
56 struct clk_hw *pgate_hw = &flexgen->pgate.hw; in flexgen_enable()
57 struct clk_hw *fgate_hw = &flexgen->fgate.hw; in flexgen_enable()
66 pr_debug("%s: flexgen output enabled\n", clk_hw_get_name(hw)); in flexgen_enable()
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/linux/drivers/net/ethernet/intel/igb/
H A De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
271 /* 1000/H is not supported, nor spec-compliant. */
305 #define E1000_TCTL_EN 0x00000002 /* enable tx */
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/linux/drivers/media/rc/
H A Dene_ir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define ENE_STATUS 0 /* hardware status - unused */
25 #define ENE_FW1_TXIRQ 0x02 /* TX interrupt pending */
39 #define ENE_FW2_EMMITER1_CONN 0x10 /* TX emmiter 1 connected */
40 #define ENE_FW2_EMMITER2_CONN 0x20 /* TX emmiter 2 connected */
43 #define ENE_FW2_LEARNING 0x80 /* hardware supports learning and TX */
56 #define ENE_GPIOFS1_GPIO0D 0x20 /* enable tx output on GPIO0D */
58 #define ENE_GPIOFS8_GPIO41 0x02 /* enable tx output on GPIO40 */
78 /* CIR Config register #1 */
85 #define ENE_CIRCFG_TX_EN 0x10 /* TX enable */
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/linux/sound/soc/tegra/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 config SND_SOC_TEGRA
5 tristate "SoC Audio for the Tegra System-on-Chip"
16 config SND_SOC_TEGRA20_AC97
25 config SND_SOC_TEGRA20_DAS
32 config SND_SOC_TEGRA20_I2S
40 config SND_SOC_TEGRA20_SPDIF
47 config SND_SOC_TEGRA30_AHUB
54 config SND_SOC_TEGRA30_I2S
62 config SND_SOC_TEGRA210_AHUB
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/linux/drivers/net/ethernet/sun/
H A Dsunbmac.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-mem size (64K) */
43 #define CREG_TXDS 0x0cUL /* TX descriptor ring ptr */
45 #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
50 #define CREG_TXWBUFPTR 0x28UL /* Local memory tx write ptr */
51 #define CREG_TXRBUFPTR 0x2cUL /* Local memory tx read ptr */
59 #define CREG_STAT_TXDERROR 0x00080000 /* TX Descriptor is bogus */
76 #define CREG_QMASK_TXLERR 0x00040000 /* TX late error */
77 #define CREG_QMASK_TXPERR 0x00020000 /* TX parity error */
78 #define CREG_QMASK_TXSERR 0x00010000 /* TX sbus error ack */
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H A Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
70 TX FIFO */
72 TX FIFO. i.e.,
73 TX Kick == TX complete. if
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/linux/drivers/net/wireless/intel/iwlwifi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 config IWLWIFI
3 tristate "Intel Wireless WiFi Next Gen AGN - Wireless-N/Advanced-N/Ultimate-N (iwlwifi) "
10 Intel Wireless WiFi Link Next-Gen AGN
14 Intel 6000 Series Wi-Fi Adapters (6200AGN and 6300AGN)
18 Intel 6005 Series Wi-Fi Adapters
19 Intel 6030 Series Wi-Fi Adapters
21 Intel 100 Series Wi-Fi Adapters (100BGN and 130BGN)
22 Intel 2000 Series Wi-Fi Adapters
23 Intel 7260 Wi-Fi Adapter
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/linux/samples/pktgen/
H A Dparameters.sh2 # SPDX-License-Identifier: GPL-2.0
8 echo "Usage: $0 [-vx] -i ethX"
9 echo " -i : (\$DEV) output interface/device (required)"
10 echo " -s : (\$PKT_SIZE) packet size"
11 echo " -d : (\$DEST_IP) destination IP. CIDR (e.g. 198.18.0.0/15) is also allowed"
12 echo " -m : (\$DST_MAC) destination MAC-addr"
13 echo " -p : (\$DST_PORT) destination PORT range (e.g. 433-444) is also allowed"
14 echo " -k : (\$UDP_CSUM) enable UDP tx checksum"
15 echo " -t : (\$THREADS) threads to start"
16 echo " -f : (\$F_THREAD) index of first thread (zero indexed CPU number)"
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/linux/include/linux/bcma/
H A Dbcma_driver_pci.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define BCMA_CORE_PCI_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */
13 #define BCMA_CORE_PCI_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */
57 #define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */
58 #define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */
81 #define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
86 #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
87 #define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
88 #define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
89 #define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
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/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
30 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
47 * +--------------+ +--------------+
49 * *--------------+ +--------------+
52 * +--------------+ +--------------+
54 * *--------------+ +--------------+
58 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
61 * 2^43 * 10^-9 / 3600 = 2.4 hours
89 * represents units of 2^-32 nanoseconds, and uses 31 bits for this, with the
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