Lines Matching +full:tx +full:- +full:output +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-flexgen.c
5 * Copyright (C) ST-Microelectronics SA 2013
6 * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
10 #include <linux/clk-provider.h>
36 /* Pre-divisor's gate */
38 /* Pre-divisor */
56 struct clk_hw *pgate_hw = &flexgen->pgate.hw; in flexgen_enable()
57 struct clk_hw *fgate_hw = &flexgen->fgate.hw; in flexgen_enable()
66 pr_debug("%s: flexgen output enabled\n", clk_hw_get_name(hw)); in flexgen_enable()
73 struct clk_hw *fgate_hw = &flexgen->fgate.hw; in flexgen_disable()
80 pr_debug("%s: flexgen output disabled\n", clk_hw_get_name(hw)); in flexgen_disable()
86 struct clk_hw *fgate_hw = &flexgen->fgate.hw; in flexgen_is_enabled()
99 struct clk_hw *mux_hw = &flexgen->mux.hw; in flexgen_get_parent()
109 struct clk_hw *mux_hw = &flexgen->mux.hw; in flexgen_set_parent()
128 div = clk_best_div(req->best_parent_rate, req->rate); in flexgen_determine_rate()
131 req->best_parent_rate = req->rate * div; in flexgen_determine_rate()
135 req->rate = req->best_parent_rate / div; in flexgen_determine_rate()
143 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; in flexgen_recalc_rate()
144 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw; in flexgen_recalc_rate()
159 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; in flexgen_set_rate()
160 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw; in flexgen_set_rate()
161 struct clk_hw *sync_hw = &flexgen->sync.hw; in flexgen_set_rate()
162 struct clk_gate *config = to_clk_gate(sync_hw); in flexgen_set_rate() local
170 if (flexgen->control_mode) { in flexgen_set_rate()
171 reg = readl(config->reg); in flexgen_set_rate()
172 reg &= ~BIT(config->bit_idx); in flexgen_set_rate()
173 writel(reg, config->reg); in flexgen_set_rate()
218 return ERR_PTR(-ENOMEM); in clk_register_flexgen()
230 /* Crossbar element config */ in clk_register_flexgen()
231 fgxbar->mux.lock = lock; in clk_register_flexgen()
232 fgxbar->mux.mask = BIT(6) - 1; in clk_register_flexgen()
233 fgxbar->mux.reg = xbar_reg; in clk_register_flexgen()
234 fgxbar->mux.shift = xbar_shift; in clk_register_flexgen()
235 fgxbar->mux.table = NULL; in clk_register_flexgen()
238 /* Pre-divider's gate config (in xbar register)*/ in clk_register_flexgen()
239 fgxbar->pgate.lock = lock; in clk_register_flexgen()
240 fgxbar->pgate.reg = xbar_reg; in clk_register_flexgen()
241 fgxbar->pgate.bit_idx = xbar_shift + 6; in clk_register_flexgen()
243 /* Pre-divider config */ in clk_register_flexgen()
244 fgxbar->pdiv.lock = lock; in clk_register_flexgen()
245 fgxbar->pdiv.reg = reg + 0x58 + idx * 4; in clk_register_flexgen()
246 fgxbar->pdiv.width = 10; in clk_register_flexgen()
248 /* Final divider's gate config */ in clk_register_flexgen()
249 fgxbar->fgate.lock = lock; in clk_register_flexgen()
250 fgxbar->fgate.reg = fdiv_reg; in clk_register_flexgen()
251 fgxbar->fgate.bit_idx = 6; in clk_register_flexgen()
253 /* Final divider config */ in clk_register_flexgen()
254 fgxbar->fdiv.lock = lock; in clk_register_flexgen()
255 fgxbar->fdiv.reg = fdiv_reg; in clk_register_flexgen()
256 fgxbar->fdiv.width = 6; in clk_register_flexgen()
258 /* Final divider sync config */ in clk_register_flexgen()
259 fgxbar->sync.lock = lock; in clk_register_flexgen()
260 fgxbar->sync.reg = fdiv_reg; in clk_register_flexgen()
261 fgxbar->sync.bit_idx = 7; in clk_register_flexgen()
263 fgxbar->control_mode = mode; in clk_register_flexgen()
265 fgxbar->hw.init = &init; in clk_register_flexgen()
267 clk = clk_register(NULL, &fgxbar->hw); in clk_register_flexgen()
308 { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
318 { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
319 { .name = "clk-ic-lmi1", .flags = CLK_IS_CRITICAL },
328 { .name = "clk-icn-gpu", },
329 { .name = "clk-fdma", },
330 { .name = "clk-nand", },
331 { .name = "clk-hva", },
332 { .name = "clk-proc-stfe", },
333 { .name = "clk-proc-tp", },
334 { .name = "clk-rx-icn-dmu", },
335 { .name = "clk-rx-icn-hva", },
337 { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
339 { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
340 { .name = "clk-mmc-0", },
341 { .name = "clk-mmc-1", },
342 { .name = "clk-jpegdec", },
344 { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
345 { .name = "clk-ic-bdisp-0", },
346 { .name = "clk-ic-bdisp-1", },
347 { .name = "clk-pp-dmu", },
348 { .name = "clk-vid-dmu", },
349 { .name = "clk-dss-lpc", },
350 { .name = "clk-st231-aud-0", },
351 { .name = "clk-st231-gp-1", },
352 { .name = "clk-st231-dmu", },
354 { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
355 { .name = "clk-tx-icn-disp-1", },
357 { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
358 { .name = "clk-stfe-frc2", },
359 { .name = "clk-eth-phy", },
360 { .name = "clk-eth-ref-phyclk", },
361 { .name = "clk-flash-promip", },
362 { .name = "clk-main-disp", },
363 { .name = "clk-aux-disp", },
364 { .name = "clk-compo-dvp", },
373 { .name = "clk-icn-gpu", },
374 { .name = "clk-fdma", },
375 { .name = "clk-nand", },
376 { .name = "clk-hva", },
377 { .name = "clk-proc-stfe", },
378 { .name = "clk-proc-tp", },
379 { .name = "clk-rx-icn-dmu", },
380 { .name = "clk-rx-icn-hva", },
382 { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
384 { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
385 { .name = "clk-mmc-0", },
386 { .name = "clk-mmc-1", },
387 { .name = "clk-jpegdec", },
389 { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
390 { .name = "clk-ic-bdisp-0", },
391 { .name = "clk-ic-bdisp-1", },
392 { .name = "clk-pp-dmu", },
393 { .name = "clk-vid-dmu", },
394 { .name = "clk-dss-lpc", },
395 { .name = "clk-st231-aud-0", },
396 { .name = "clk-st231-gp-1", },
397 { .name = "clk-st231-dmu", },
399 { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
400 { .name = "clk-tx-icn-disp-1", },
402 { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
403 { .name = "clk-stfe-frc2", },
404 { .name = "clk-eth-phy", },
405 { .name = "clk-eth-ref-phyclk", },
406 { .name = "clk-flash-promip", },
407 { .name = "clk-main-disp", },
408 { .name = "clk-aux-disp", },
409 { .name = "clk-compo-dvp", },
410 { .name = "clk-tx-icn-hades", },
411 { .name = "clk-rx-icn-hades", },
413 { .name = "clk-icn-reg-16", .flags = CLK_IS_CRITICAL },
414 { .name = "clk-pp-hades", },
415 { .name = "clk-clust-hades", },
416 { .name = "clk-hwpe-hades", },
417 { .name = "clk-fc-hades", },
426 { .name = "clk-icn-gpu", },
427 { .name = "clk-fdma", },
428 { .name = "clk-nand", },
429 { .name = "clk-hva", },
430 { .name = "clk-proc-stfe", },
431 { .name = "clk-tp", },
433 { .name = "clk-rx-icn-dmu", .flags = CLK_IS_CRITICAL },
435 { .name = "clk-rx-icn-hva", .flags = CLK_IS_CRITICAL },
436 { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
438 { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
439 { .name = "clk-mmc-0", },
440 { .name = "clk-mmc-1", },
441 { .name = "clk-jpegdec", },
443 { .name = "clk-icn-reg", .flags = CLK_IS_CRITICAL },
444 { .name = "clk-proc-bdisp-0", },
445 { .name = "clk-proc-bdisp-1", },
446 { .name = "clk-pp-dmu", },
447 { .name = "clk-vid-dmu", },
448 { .name = "clk-dss-lpc", },
449 { .name = "clk-st231-aud-0", },
450 { .name = "clk-st231-gp-1", },
451 { .name = "clk-st231-dmu", },
453 { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
455 { .name = "clk-tx-icn-1", .flags = CLK_IS_CRITICAL },
457 { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
458 { .name = "clk-stfe-frc2", },
459 { .name = "clk-eth-phyref", },
460 { .name = "clk-eth-ref-phyclk", },
461 { .name = "clk-flash-promip", },
462 { .name = "clk-main-disp", },
463 { .name = "clk-aux-disp", },
464 { .name = "clk-compo-dvp", },
466 { .name = "clk-tx-icn-hades", .flags = CLK_IS_CRITICAL },
468 { .name = "clk-rx-icn-hades", .flags = CLK_IS_CRITICAL },
470 { .name = "clk-icn-reg-16", .flags = CLK_IS_CRITICAL },
471 { .name = "clk-pp-hevc", },
472 { .name = "clk-clust-hevc", },
473 { .name = "clk-hwpe-hevc", },
474 { .name = "clk-fc-hevc", },
475 { .name = "clk-proc-mixer", },
476 { .name = "clk-proc-sc", },
477 { .name = "clk-avsp-hevc", },
486 { .name = "clk-pcm-0", },
487 { .name = "clk-pcm-1", },
488 { .name = "clk-pcm-2", },
489 { .name = "clk-spdiff", },
499 { .name = "clk-pcm-0", },
500 { .name = "clk-pcm-1", },
501 { .name = "clk-pcm-2", },
502 { .name = "clk-spdiff", },
503 { .name = "clk-pcmr10-master", },
504 { .name = "clk-usb2-phy", },
514 { .name = "clk-pix-main-disp", },
515 { .name = "clk-pix-pip", },
516 { .name = "clk-pix-gdp1", },
517 { .name = "clk-pix-gdp2", },
518 { .name = "clk-pix-gdp3", },
519 { .name = "clk-pix-gdp4", },
520 { .name = "clk-pix-aux-disp", },
521 { .name = "clk-denc", },
522 { .name = "clk-pix-hddac", },
523 { .name = "clk-hddac", },
524 { .name = "clk-sddac", },
525 { .name = "clk-pix-dvo", },
526 { .name = "clk-dvo", },
527 { .name = "clk-pix-hdmi", },
528 { .name = "clk-tmds-hdmi", },
529 { .name = "clk-ref-hdmiphy", },
540 { .name = "clk-pix-main-disp", },
545 { .name = "clk-tmds-hdmi-div2", },
546 { .name = "clk-pix-aux-disp", },
547 { .name = "clk-denc", },
548 { .name = "clk-pix-hddac", },
549 { .name = "clk-hddac", },
550 { .name = "clk-sddac", },
551 { .name = "clk-pix-dvo", },
552 { .name = "clk-dvo", },
553 { .name = "clk-pix-hdmi", },
554 { .name = "clk-tmds-hdmi", },
555 { .name = "clk-ref-hdmiphy", },
564 { .name = "clk-vp9", },
575 { .name = "clk-stfe-frc1", },
576 { .name = "clk-tsout-0", },
577 { .name = "clk-tsout-1", },
578 { .name = "clk-mchi", },
579 { .name = "clk-vsens-compo", },
580 { .name = "clk-frc1-remote", },
581 { .name = "clk-lpc-0", },
582 { .name = "clk-lpc-1", },
592 .compatible = "st,flexgen-audio",
596 .compatible = "st,flexgen-video",
600 .compatible = "st,flexgen-stih407-a0",
604 .compatible = "st,flexgen-stih410-a0",
608 .compatible = "st,flexgen-stih407-c0",
612 .compatible = "st,flexgen-stih410-c0",
616 .compatible = "st,flexgen-stih418-c0",
620 .compatible = "st,flexgen-stih407-d0",
624 .compatible = "st,flexgen-stih410-d0",
628 .compatible = "st,flexgen-stih407-d2",
632 .compatible = "st,flexgen-stih418-d2",
636 .compatible = "st,flexgen-stih407-d3",
674 data = (struct clkgen_data *)match->data; in st_of_flexgen_setup()
675 flex_flags = data->flags; in st_of_flexgen_setup()
676 clk_mode = data->mode; in st_of_flexgen_setup()
683 /* First try to get output information from the compatible data */ in st_of_flexgen_setup()
684 if (!data || !data->outputs_nb || !data->outputs) { in st_of_flexgen_setup()
685 ret = of_property_count_strings(np, "clock-output-names"); in st_of_flexgen_setup()
687 pr_err("%s: Failed to get number of output clocks (%d)", in st_of_flexgen_setup()
688 __func__, clk_data->clk_num); in st_of_flexgen_setup()
691 clk_data->clk_num = ret; in st_of_flexgen_setup()
693 clk_data->clk_num = data->outputs_nb; in st_of_flexgen_setup()
695 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *), in st_of_flexgen_setup()
697 if (!clk_data->clks) in st_of_flexgen_setup()
706 for (i = 0; i < clk_data->clk_num; i++) { in st_of_flexgen_setup()
709 if (!data || !data->outputs_nb || !data->outputs) { in st_of_flexgen_setup()
711 "clock-output-names", in st_of_flexgen_setup()
717 clk_name = data->outputs[i].name; in st_of_flexgen_setup()
718 flex_flags = data->flags | data->outputs[i].flags; in st_of_flexgen_setup()
722 * If we read an empty clock name then the output is unused in st_of_flexgen_setup()
733 clk_data->clks[i] = clk; in st_of_flexgen_setup()
744 kfree(clk_data->clks); in st_of_flexgen_setup()