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Searched +full:tsa +full:- +full:serial (Results 1 – 15 of 15) sorted by relevance

/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-scc-qmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
14 serial controller using the same TDM physical interface routed from TSA.
19 - enum:
20 - fsl,mpc885-scc-qmc
21 - fsl,mpc866-scc-qmc
22 - const: fsl,cpm1-scc-qmc
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H A Dfsl,qe-ucc-qmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
14 serial controller using the same TDM physical interface routed from TSA.
19 - enum:
20 - fsl,mpc8321-ucc-qmc
21 - const: fsl,qe-ucc-qmc
25 - description: UCC (Unified communication controller) register base
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H A Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
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H A Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
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/linux/drivers/soc/fsl/qe/
H A Dtsa.c1 // SPDX-License-Identifier: GPL-2.0
3 * TSA driver
10 #include "tsa.h"
11 #include <dt-bindings/soc/cpm1-fsl,tsa.h>
12 #include <dt-bindings/soc/qe-fsl,tsa.h>
23 /* TSA SI RAM routing tables entry (CPM1) */
36 /* TSA SI RAM routing tables entry (QE) */
51 * - CPM1: 32bit register split in 2*16bit (16bit TDM)
52 * - QE: 4x16bit registers, one per TDM
157 struct tsa { struct
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H A Dtsa.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * TSA management
25 /* Connect and disconnect the TSA serial */
42 /* Get serial number */
H A Dqmc.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/dma-mapping.h>
26 #include "tsa.h"
64 /* Tx time-slot assignment table pointer (16 bits) */
76 /* Rx time-slot assignment table pointer (16 bits) */
92 /* A reserved area (0xB0 -> 0xC3) that must be initialized to 0 (QE only) */
98 /* TSA entry (16bit entry in TSATRX and TSATTX) */
129 /* Zero-insertion state (32 bits) */
322 return qmc->data->version == QMC_QE; in qmc_is_qe()
333 /* Retrieve info from the TSA related serial */ in qmc_chan_get_info()
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/linux/Documentation/devicetree/bindings/media/
H A Dstih407-c8sectpfe.txt14 - compatible : Should be "stih407-c8sectpfe"
16 - reg : Address and length of register sets for each device in
17 "reg-names"
19 - reg-names : The names of the register addresses corresponding to the
21 - c8sectpfe: c8sectpfe registers
22 - c8sectpfe-ram: c8sectpfe internal sram
24 - clocks : phandle list of c8sectpfe clocks
25 - clock-names : should be "c8sectpfe"
26 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
28 - pinctrl-names : a pinctrl state named tsin%d-serial or tsin%d-parallel (where %d is tsin-num)
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/linux/arch/arm/boot/dts/st/
H A Dstihxxx-b2120.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/clock/stih407-clks.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/media/c8sectpfe.h>
11 compatible = "gpio-leds";
12 led-red {
15 linux,default-trigger = "heartbeat";
17 led-green {
19 default-state = "off";
24 compatible = "simple-audio-card";
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/linux/drivers/s390/block/
H A Ddasd_eckd.c1 // SPDX-License-Identifier: GPL-2.0
134 /* set ECKD specific ccw-device options */ in dasd_eckd_probe()
140 "ccw-device options"); in dasd_eckd_probe()
163 return (d1 + (d2 - 1)) / d2; in ceil_quot()
172 switch (rdc->dev_type) { in recs_per_track()
201 geo->cyl = (__u16) cyl; in set_ch_t()
202 geo->head = cyl >> 16; in set_ch_t()
203 geo->head <<= 4; in set_ch_t()
204 geo->head |= head; in set_ch_t()
214 struct dasd_eckd_private *private = device->private; in dasd_eckd_track_from_irb()
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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/linux/drivers/net/ethernet/sfc/siena/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2023, Intel Corporation. */
44 static int debug = -1;
56 * ice_hw_to_dev - Get device pointer from the hardware structure
67 return &pf->pdev->dev; in ice_hw_to_dev()
90 return dev && (dev->netdev_ops == &ice_netdev_ops || in netif_is_ice()
91 dev->netdev_ops == &ice_netdev_safe_mode_ops); in netif_is_ice()
95 * ice_get_tx_pending - returns number of Tx descriptors not processed
102 head = ring->next_to_clean; in ice_get_tx_pending()
103 tail = ring->next_to_use; in ice_get_tx_pending()
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/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
31 static const char i40e_copyright[] = "Copyright (c) 2013 - 2019 Intel Corporation.";
57 /* i40e_pci_tbl - PCI Device ID Table
97 static int debug = -1;
116 if (is_unicast_ether_addr(f->macaddr) || is_link_local_ether_addr(f->macaddr)) in netdev_hw_addr_refcnt()
117 ha_list = &netdev->uc; in netdev_hw_addr_refcnt()
119 ha_list = &netdev->mc; in netdev_hw_addr_refcnt()
122 if (ether_addr_equal(ha->addr, f->macaddr)) { in netdev_hw_addr_refcnt()
123 ha->refcount += delta; in netdev_hw_addr_refcnt()
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