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/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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H A Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
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/linux/mm/
H A Dhuge_memory.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/backing-dev.h>
39 #include <linux/memory-tiers.h>
44 #include <asm/tlb.h>
93 if (!vma->vm_file) in file_thp_enabled()
96 inode = file_inode(vma->vm_file); in file_thp_enabled()
98 return !inode_is_open_for_write(inode) && S_ISREG(inode->i_mode); in file_thp_enabled()
123 if (!vma->vm_mm) /* vdso */ in __thp_vma_allowable_orders()
153 addr = vma->vm_end - (PAGE_SIZE << order); in __thp_vma_allowable_orders()
168 if (!in_pf && shmem_file(vma->vm_file)) in __thp_vma_allowable_orders()
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H A Dmapping_dirty_helpers.c1 // SPDX-License-Identifier: GPL-2.0
11 * struct wp_walk - Private struct for pagetable walk callbacks
25 * wp_pte - Write-protect a pte
31 * The function write-protects a pte and records the range in
32 * virtual address space of touched ptes for efficient range TLB flushes.
37 struct wp_walk *wpwalk = walk->private; in wp_pte()
41 pte_t old_pte = ptep_modify_prot_start(walk->vma, addr, pte); in wp_pte()
44 ptep_modify_prot_commit(walk->vma, addr, pte, old_pte, ptent); in wp_pte()
45 wpwalk->total++; in wp_pte()
46 wpwalk->tlbflush_start = min(wpwalk->tlbflush_start, addr); in wp_pte()
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H A Dmprotect.c1 // SPDX-License-Identifier: GPL-2.0
34 #include <linux/memory-tiers.h>
39 #include <asm/tlb.h>
48 if (WARN_ON_ONCE(!(vma->vm_flags & VM_WRITE))) in can_change_pte_writable()
59 /* Do we need write faults for uffd-wp tracking? */ in can_change_pte_writable()
63 if (!(vma->vm_flags & VM_SHARED)) { in can_change_pte_writable()
65 * Writable MAP_PRIVATE mapping: We can only special-case on in can_change_pte_writable()
67 * write-fault handler similarly would map them writable without in can_change_pte_writable()
78 * needs a real write-fault for writenotify in can_change_pte_writable()
81 * just like the write-fault handler would do. in can_change_pte_writable()
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H A Dmadvise.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/page-isolation.h>
28 #include <linux/backing-dev.h>
35 #include <asm/tlb.h>
42 * and return -ERESTARTNOINTR to have userspace try again.
47 struct mmu_gather *tlb; member
53 struct mmu_gather *tlb; member
57 * Any behaviour which results in changes to the vma->vm_flags needs to
89 /* Add 1 for NUL terminator at the end of the anon_name->name */ in anon_vma_name_alloc()
93 kref_init(&anon_name->kref); in anon_vma_name_alloc()
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/linux/include/linux/
H A Dhuge_mm.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 bool madvise_free_huge_pmd(struct mmu_gather *tlb, struct vm_area_struct *vma,
30 int zap_huge_pmd(struct mmu_gather *tlb, struct vm_area_struct *vma, pmd_t *pmd,
32 int zap_huge_pud(struct mmu_gather *tlb, struct vm_area_struct *vma, pud_t *pud,
36 int change_huge_pmd(struct mmu_gather *tlb, struct vm_area_struct *vma,
74 * and including PMD_ORDER, except order-0 (which is not "huge") and order-1
77 #define THP_ORDERS_ALL_ANON ((BIT(PMD_ORDER + 1) - 1) & ~(BIT(0) | BIT(1)))
81 * file is never split and the MAX_PAGECACHE_ORDER limit does not apply to
87 ((BIT(MAX_PAGECACHE_ORDER + 1) - 1) & ~BIT(0))
112 #define HPAGE_PMD_ORDER (HPAGE_PMD_SHIFT-PAGE_SHIFT)
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H A Dio-pgtable.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 * struct iommu_flush_ops - IOMMU callbacks for TLB and page table management.
28 * @tlb_flush_all: Synchronously invalidate the entire TLB context.
29 * @tlb_flush_walk: Synchronously invalidate all intermediate TLB state
32 * @tlb_add_page: Optional callback to queue up leaf TLB invalidation for a
33 * single page. IOMMUs that cannot batch TLB invalidation
50 * struct io_pgtable_cfg - Configuration data for a set of page tables.
53 * action by the low-level page table allocator.
60 * @tlb: TLB management callbacks for this set of tables.
68 * even in non-secure state where they should normally be ignored.
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/linux/Documentation/admin-guide/mm/
H A Dtranshuge.rst26 requiring larger clear-page copy-page in page faults which is a
36 1) the TLB miss will run faster (especially with virtualization using
40 2) a single TLB entry will be mapping a much larger amount of virtual
41 memory in turn reducing the number of TLB misses. With
42 virtualization and nested pagetables the TLB can be mapped of
45 the two is using hugepages just because of the fact the TLB miss is
48 Modern kernels support "multi-size THP" (mTHP), which introduces the
50 but smaller than traditional PMD-size (as described above), in
51 increments of a power-of-2 number of pages. mTHP can back anonymous
53 PTE-mapped, but in many cases can still provide similar benefits to
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/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
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/linux/arch/arm/mm/
H A Dtlb-v4wb.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 4 TLB handling functions.
8 * These assume a split I/D TLBs w/o I TLB entry, with a write buffer.
16 #include <asm/asm-offsets.h>
18 #include "proc-macros.S"
24 * Invalidate a range of TLB entries in the specified address space.
26 * - start - range start address
27 * - end - range end address
28 * - mm - mm_struct describing address space
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H A Dtlb-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/tlb-v7.S
5 * Copyright (C) 1997-2002 Russell King
8 * ARM architecture version 6 TLB handling functions.
9 * These assume a split I/D TLB.
15 #include <asm/asm-offsets.h>
18 #include "proc-macros.S"
20 .arch armv7-a
25 * Invalidate a range of TLB entries in the specified address space.
27 * - start - start address (may not be aligned)
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H A Dtlb-v4wbi.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 4 and version 5 TLB handling functions.
8 * These assume a split I/D TLBs, with a write buffer.
16 #include <asm/asm-offsets.h>
18 #include "proc-macros.S"
23 * Invalidate a range of TLB entries in the specified address space.
25 * - start - range start address
26 * - end - range end address
27 * - mm - mm_struct describing address space
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H A Dtlb-v6.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/tlb-v6.S
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 6 TLB handling functions.
8 * These assume a split I/D TLB.
13 #include <asm/asm-offsets.h>
17 #include "proc-macros.S"
26 * Invalidate a range of TLB entries in the specified address space.
28 * - start - start address (may not be aligned)
29 * - end - end address (exclusive, may not be aligned)
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H A Dtlb-v4.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 4 TLB handling functions.
8 * These assume a split I/D TLBs, and no write buffer.
16 #include <asm/asm-offsets.h>
18 #include "proc-macros.S"
24 * Invalidate a range of TLB entries in the specified user address space.
26 * - start - range start address
27 * - end - range end address
28 * - mm - mm_struct describing address space
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/linux/arch/mips/mm/
H A Dtlbex.c6 * Synthesize TLB refill handlers at runtime.
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
34 #include <asm/cpu-type.h>
54 * TLB load/store/modify handlers.
133 * CVMSEG starts at address -32768 and extends for in scratchpad_offset()
137 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; in scratchpad_offset()
232 * TLB exception handlers.
264 unsigned int count = (end - start) / sizeof(u32); in dump_handler()
288 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
319 return -1; in allocate_kscratch()
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/linux/arch/sh/mm/
H A Dtlb-pteaex.c2 * arch/sh/mm/tlb-pteaex.c
4 * TLB operations for SH-X3 CPUs featuring PTE ASID Extensions.
25 if (vma && current->active_mm != vma->vm_mm) in __update_tlb()
42 * For the extended mode TLB this is trivial, only the ESZ and in __update_tlb()
44 * the protection bits (with the exception of the compat-mode SZ in __update_tlb()
58 /* Load the TLB */ in __update_tlb()
64 * While SH-X2 extended TLB mode splits out the memory-mapped I/UTLB
65 * data arrays, SH-X3 cores with PTEAEX split out the memory-mapped
67 * in extended mode, the legacy 8-bit ASID field in address array 1 has
86 * Flush all the TLB. in local_flush_tlb_all()
/linux/arch/arm64/include/asm/
H A Dkvm_pgtable.h1 // SPDX-License-Identifier: GPL-2.0-only
14 #define KVM_PGTABLE_FIRST_LEVEL -1
18 * The largest supported block sizes for KVM (no 52-bit PA support):
19 * - 4K (level 1): 1GB
20 * - 16K (level 2): 32MB
21 * - 64K (level 2): 512MB
60 #define KVM_PHYS_INVALID (-1ULL)
104 * Used to indicate a pte for which a 'break-before-make' sequence is in
189 * struct kvm_pgtable_mm_ops - Memory management callbacks.
231 * enum kvm_pgtable_stage2_flags - Stage-2 page-table flags.
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/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/linux/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/linux/Documentation/admin-guide/hw-vuln/
H A Dmultihit.rst6 instruction fetch hits multiple entries in the instruction TLB. This can
13 -------------------
18 - non-Intel processors
20 - Some Atoms (Airmont, Bonnell, Goldmont, GoldmontPlus, Saltwell, Silvermont)
22 - Intel processors that have the PSCHANGE_MC_NO bit set in the
27 ------------
32 CVE-2018-12207 Machine Check Error Avoidance on Page Size Change
37 -------
42 the illusion of a very large memory for processors. This virtual space is split
47 processors include a structure, called TLB, that caches recent translations.
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/linux/arch/mips/kvm/
H A Dtlb.c6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
7 * TLB handlers run from KSEG0
26 #include <asm/tlb.h>
42 struct mm_struct *gpa_mm = &vcpu->kvm->arch.gpa_mm; in kvm_mips_get_root_asid()
79 * clear_root_gid() - Set GuestCtl1.RID for normal root operation.
90 * set_root_gid_to_guest_gid() - Set GuestCtl1.RID to match GuestCtl1.ID.
92 * Sets the root GuestID to match the current guest GuestID, for TLB operation
93 * on the GPA->RPA mappings in the root TLB.
96 * possibly longer if TLB registers are modified.
121 /* Set root GuestID for root probe and write of guest TLB entry */ in kvm_vz_host_tlb_inv()
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/linux/arch/x86/mm/pat/
H A Dset_memory.c1 // SPDX-License-Identifier: GPL-2.0-only
39 * The current flushing context - we pass it instead of 5 arguments:
66 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
99 direct_pages_count[level]--; in split_page_count()
106 direct_pages_count[level - 1] += PTRS_PER_PTE; in split_page_count()
118 direct_pages_count[level - 1] -= PTRS_PER_PTE; in collapse_page_count()
190 seq_printf(m, "4K pages set-checked: %16lu\n", cpa_4k_install); in cpastats_show()
244 * points to #2, but almost all physical-to-virtual translations point to #1.
261 return __pa_symbol(roundup(_brk_end, PMD_SIZE) - 1) >> PAGE_SHIFT; in highmap_end_pfn()
277 /* There is no highmap on 32-bit */ in __cpa_pfn_in_highmap()
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/linux/arch/alpha/kernel/
H A Derr_marvel.c1 // SPDX-License-Identifier: GPL-2.0
49 env = lf_subpackets->env[ev7_lf_env_index(ev_packets[i].type)]; in marvel_print_680_frame()
56 env->cabinet, in marvel_print_680_frame()
57 env->drawer); in marvel_print_680_frame()
58 printk("%s Module Type: 0x%x - Unit ID 0x%x - " in marvel_print_680_frame()
61 env->module_type, in marvel_print_680_frame()
62 env->unit_id, in marvel_print_680_frame()
63 env->condition); in marvel_print_680_frame()
77 if (lf_subpackets->env[i]) in marvel_process_680_frame()
317 "%s Source Port: %lld - Dest PID: %lld - OpCode: %s\n", in marvel_print_po7_ugbge_sym()
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/linux/arch/powerpc/perf/
H A De500-pmu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
30 * Table of generalized cache-related events.
31 * 0 means not supported, -1 means nonsensical, other values
36 * D-cache misses are not split into read/write/prefetch;
46 [C(OP_WRITE)] = { -1, -1 },
62 * the chip's internal level-one TLB which is probably not
63 * what the user wants. Instead, unified level-two TLB misses
68 [C(OP_WRITE)] = { -1, -1 },
69 [C(OP_PREFETCH)] = { -1, -1 },
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