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/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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H A Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
[all …]
/linux/mm/
H A Dhuge_memory.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/backing-dev.h>
39 #include <linux/memory-tiers.h>
45 #include <asm/tlb.h>
92 if (!vma->vm_file) in file_thp_enabled()
95 inode = file_inode(vma->vm_file); in file_thp_enabled()
100 if (!mapping_pmd_folio_support(vma->vm_fil in file_thp_enabled()
2342 madvise_free_huge_pmd(struct mmu_gather * tlb,struct vm_area_struct * vma,pmd_t * pmd,unsigned long addr,unsigned long next) madvise_free_huge_pmd() argument
2487 zap_huge_pmd(struct mmu_gather * tlb,struct vm_area_struct * vma,pmd_t * pmd,unsigned long addr) zap_huge_pmd() argument
2660 change_huge_pmd(struct mmu_gather * tlb,struct vm_area_struct * vma,pmd_t * pmd,unsigned long addr,pgprot_t newprot,unsigned long cp_flags) change_huge_pmd() argument
2761 change_huge_pud(struct mmu_gather * tlb,struct vm_area_struct * vma,pud_t * pudp,unsigned long addr,pgprot_t newprot,unsigned long cp_flags) change_huge_pud() argument
2956 zap_huge_pud(struct mmu_gather * tlb,struct vm_area_struct * vma,pud_t * pud,unsigned long addr) zap_huge_pud() argument
4517 int split = 0, i; deferred_split_scan() local
4642 unsigned long total = 0, split = 0; split_huge_pages_all() local
4707 unsigned long total = 0, split = 0; split_huge_pages_pid() local
4825 unsigned long total = 0, split = 0; split_huge_pages_in_file() local
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H A Dmapping_dirty_helpers.c1 // SPDX-License-Identifier: GPL-2.0
11 * struct wp_walk - Private struct for pagetable walk callbacks
25 * wp_pte - Write-protect a pte
31 * The function write-protects a pte and records the range in
32 * virtual address space of touched ptes for efficient range TLB flushes.
37 struct wp_walk *wpwalk = walk->private; in wp_pte()
41 pte_t old_pte = ptep_modify_prot_start(walk->vma, addr, pte); in wp_pte()
44 ptep_modify_prot_commit(walk->vma, addr, pte, old_pte, ptent); in wp_pte()
45 wpwalk->total++; in wp_pte()
46 wpwalk->tlbflush_start = min(wpwalk->tlbflush_start, addr); in wp_pte()
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H A Dmadvise.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/page-isolation.h>
29 #include <linux/backing-dev.h>
36 #include <asm/tlb.h>
41 #define __MADV_SET_ANON_VMA_NAME (-1)
45 * and return -ERESTARTNOINTR to have userspace try again.
50 struct mmu_gather *tlb; member
69 struct mmu_gather *tlb; member
359 struct mmu_gather *tlb = private->tlb; madvise_cold_or_pageout_pte_range() local
574 madvise_cold_page_range(struct mmu_gather * tlb,struct madvise_behavior * madv_behavior) madvise_cold_page_range() argument
599 struct mmu_gather tlb; madvise_cold() local
612 madvise_pageout_page_range(struct mmu_gather * tlb,struct vm_area_struct * vma,struct madvise_behavior_range * range) madvise_pageout_page_range() argument
629 struct mmu_gather tlb; madvise_pageout() local
658 struct mmu_gather *tlb = walk->private; madvise_free_pte_range() local
808 struct mmu_gather *tlb = madv_behavior->tlb; madvise_free_single_vma() local
2009 struct mmu_gather tlb; do_madvise() local
2040 struct mmu_gather tlb; vector_madvise() local
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/linux/Documentation/admin-guide/mm/
H A Dtranshuge.rst26 requiring larger clear-page copy-page in page faults which is a
36 1) the TLB miss will run faster (especially with virtualization using
40 2) a single TLB entry will be mapping a much larger amount of virtual
41 memory in turn reducing the number of TLB misses. With
42 virtualization and nested pagetables the TLB can be mapped of
45 the two is using hugepages just because of the fact the TLB miss is
48 Modern kernels support "multi-size THP" (mTHP), which introduces the
50 but smaller than traditional PMD-size (as described above), in
51 increments of a power-o
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/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cell
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/linux/arch/arm/mm/
H A Dtlb-v4wb.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 4 TLB handling functions.
8 * These assume a split I/D TLBs w/o I TLB entry, with a write buffer.
16 #include <asm/asm-offsets.h>
18 #include "proc-macros.S"
24 * Invalidate a range of TLB entries in the specified address space.
26 * - start - range start address
27 * - end - range end address
28 * - mm - mm_struct describing address space
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H A Dtlb-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/tlb-v7.S
5 * Copyright (C) 1997-2002 Russell King
8 * ARM architecture version 6 TLB handling functions.
9 * These assume a split I/D TLB.
15 #include <asm/asm-offsets.h>
18 #include "proc-macros.S"
20 .arch armv7-a
25 * Invalidate a range of TLB entries in the specified address space.
27 * - start - start address (may not be aligned)
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H A Dtlb-v4wbi.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 4 and version 5 TLB handling functions.
8 * These assume a split I/D TLBs, with a write buffer.
16 #include <asm/asm-offsets.h>
18 #include "proc-macros.S"
23 * Invalidate a range of TLB entries in the specified address space.
25 * - start - range start address
26 * - end - range end address
27 * - mm - mm_struct describing address space
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H A Dtlb-v6.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/tlb-v6.S
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 6 TLB handling functions.
8 * These assume a split I/D TLB.
13 #include <asm/asm-offsets.h>
17 #include "proc-macros.S"
26 * Invalidate a range of TLB entries in the specified address space.
28 * - start - start address (may not be aligned)
29 * - end - end address (exclusive, may not be aligned)
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H A Dtlb-v4.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 4 TLB handling functions.
8 * These assume a split I/D TLBs, and no write buffer.
16 #include <asm/asm-offsets.h>
18 #include "proc-macros.S"
24 * Invalidate a range of TLB entries in the specified user address space.
26 * - start - range start address
27 * - end - range end address
28 * - mm - mm_struct describing address space
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/linux/arch/mips/mm/
H A Dtlbex.c6 * Synthesize TLB refill handlers at runtime.
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
34 #include <asm/cpu-type.h>
54 * TLB load/store/modify handlers.
133 * CVMSEG starts at address -32768 and extends for in scratchpad_offset()
137 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; in scratchpad_offset()
232 * TLB exception handlers.
264 unsigned int count = (end - start) / sizeof(u32); in dump_handler()
288 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
319 return -1; in allocate_kscratch()
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/linux/arch/sh/mm/
H A Dtlb-pteaex.c2 * arch/sh/mm/tlb-pteaex.c
4 * TLB operations for SH-X3 CPUs featuring PTE ASID Extensions.
25 if (vma && current->active_mm != vma->vm_mm) in __update_tlb()
42 * For the extended mode TLB this is trivial, only the ESZ and in __update_tlb()
44 * the protection bits (with the exception of the compat-mode SZ in __update_tlb()
58 /* Load the TLB */ in __update_tlb()
64 * While SH-X2 extended TLB mode splits out the memory-mapped I/UTLB
65 * data arrays, SH-X3 cores with PTEAEX split out the memory-mapped
67 * in extended mode, the legacy 8-bit ASID field in address array 1 has
86 * Flush all the TLB. in local_flush_tlb_all()
/linux/tools/perf/pmu-events/arch/x86/pantherlake/
H A Dcache.json16 "PublicDescription": "Counts L0 data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
22 "BriefDescription": "Cachelines replaced into the L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
26 "PublicDescription": "Counts cachelines replaced into the L1 d-cache.",
32 "BriefDescription": "Cachelines replaced into the L0 and L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
36 "PublicDescription": "Counts cachelines replaced into the L0 and L1 d-cach
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/linux/include/linux/
H A Dio-pgtable.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 * struct iommu_flush_ops - IOMMU callbacks for TLB and page table management.
26 * @tlb_flush_all: Synchronously invalidate the entire TLB context.
27 * @tlb_flush_walk: Synchronously invalidate all intermediate TLB state
30 * @tlb_add_page: Optional callback to queue up leaf TLB invalidation for a
31 * single page. IOMMUs that cannot batch TLB invalidation
48 * struct io_pgtable_cfg - Configuration data for a set of page tables.
51 * action by the low-level page table allocator.
58 * @tlb: TLB management callbacks for this set of tables.
66 * even in non-secure state where they should normally be ignored.
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/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/linux/Documentation/admin-guide/hw-vuln/
H A Dmultihit.rst6 instruction fetch hits multiple entries in the instruction TLB. This can
13 -------------------
18 - non-Intel processors
20 - Some Atoms (Airmont, Bonnell, Goldmont, GoldmontPlus, Saltwell, Silvermont)
22 - Intel processors that have the PSCHANGE_MC_NO bit set in the
27 ------------
32 CVE-2018-12207 Machine Check Error Avoidance on Page Size Change
37 -------
42 the illusion of a very large memory for processors. This virtual space is split
47 processors include a structure, called TLB, that caches recent translations.
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/linux/tools/perf/pmu-events/arch/x86/arrowlake/
H A Dcache.json36 "PublicDescription": "Counts L0 data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
42 "BriefDescription": "Cachelines replaced into the L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
46 "PublicDescription": "Counts cachelines replaced into the L1 d-cache.",
52 "BriefDescription": "Cachelines replaced into the L0 and L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
56 "PublicDescription": "Counts cachelines replaced into the L0 and L1 d-cach
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/linux/arch/mips/kvm/
H A Dtlb.c6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
7 * TLB handlers run from KSEG0
26 #include <asm/tlb.h>
42 struct mm_struct *gpa_mm = &vcpu->kvm->arch.gpa_mm; in kvm_mips_get_root_asid()
79 * clear_root_gid() - Set GuestCtl1.RID for normal root operation.
90 * set_root_gid_to_guest_gid() - Set GuestCtl1.RID to match GuestCtl1.ID.
92 * Sets the root GuestID to match the current guest GuestID, for TLB operation
93 * on the GPA->RPA mappings in the root TLB.
96 * possibly longer if TLB registers are modified.
121 /* Set root GuestID for root probe and write of guest TLB entry */ in kvm_vz_host_tlb_inv()
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/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A Dcache.json108 "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss.",
116 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
120 "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.",
125 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which missed in the L2 cache.",
467 "EventName": "MEM_UOPS_RETIRED.SPLIT",
472 "BriefDescription": "Counts the number of retired split load uops.",
481 "BriefDescription": "Counts the number of retired split store uops.",
490 "BriefDescription": "Counts the number of memory uops retired that missed in the second level TLB.",
499 "BriefDescription": "Counts the number of load uops retired that miss in the second Level TLB.",
508 "BriefDescription": "Counts the number of store uops retired that miss in the second level TLB
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/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A Dcache.json35 "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
77 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
174 "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache.",
178 "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache. These lines are typically in Shared or Exclusive state. A non-threaded event.",
198 "PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-bac
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/linux/arch/x86/mm/pat/
H A Dset_memory.c1 // SPDX-License-Identifier: GPL-2.0-only
39 * The current flushing context - we pass it instead of 5 arguments:
66 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
99 direct_pages_count[level]--; in split_page_count()
106 direct_pages_count[level - 1] += PTRS_PER_PTE; in split_page_count()
118 direct_pages_count[level - 1] -= PTRS_PER_PTE; in collapse_page_count()
190 seq_printf(m, "4K pages set-checked: %16lu\n", cpa_4k_install); in cpastats_show()
244 * points to #2, but almost all physical-to-virtual translations point to #1.
261 return __pa_symbol(roundup(_brk_end, PMD_SIZE) - 1) >> PAGE_SHIFT; in highmap_end_pfn()
277 /* There is no highmap on 32-bit */ in __cpa_pfn_in_highmap()
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/linux/arch/alpha/kernel/
H A Derr_marvel.c1 // SPDX-License-Identifier: GPL-2.0
49 env = lf_subpackets->env[ev7_lf_env_index(ev_packets[i].type)]; in marvel_print_680_frame()
56 env->cabinet, in marvel_print_680_frame()
57 env->drawer); in marvel_print_680_frame()
58 printk("%s Module Type: 0x%x - Unit ID 0x%x - " in marvel_print_680_frame()
61 env->module_type, in marvel_print_680_frame()
62 env->unit_id, in marvel_print_680_frame()
63 env->condition); in marvel_print_680_frame()
77 if (lf_subpackets->env[i]) in marvel_process_680_frame()
317 "%s Source Port: %lld - Dest PID: %lld - OpCode: %s\n", in marvel_print_po7_ugbge_sym()
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/linux/tools/perf/pmu-events/arch/x86/lunarlake/
H A Dcache.json26 "PublicDescription": "Counts L0 data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
32 "BriefDescription": "Cachelines replaced into the L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
36 "PublicDescription": "Counts cachelines replaced into the L1 d-cache.",
42 "BriefDescription": "Cachelines replaced into the L0 and L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
46 "PublicDescription": "Counts cachelines replaced into the L0 and L1 d-cach
[all...]

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