Home
last modified time | relevance | path

Searched +full:timing +full:- +full:controller (Results 1 – 25 of 497) sorted by relevance

12345678910>>...20

/linux/drivers/ata/
H A Dpata_sis.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_sis.c - SiS ATA driver
9 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
67 while (lap->device) { in sis_short_ata40()
68 if (lap->device == dev->device && in sis_short_ata40()
69 lap->subvendor == dev->subsystem_vendor && in sis_short_ata40()
70 lap->subdevice == dev->subsystem_device) in sis_short_ata40()
79 * sis_old_port_base - return PCI configuration base for dev
88 return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); in sis_old_port_base()
92 * sis_port_base - return PCI configuration base for dev
[all …]
H A Dpata_legacy.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pata-legacy.c - Legacy port PATA/SATA controller driver.
9 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
21 * Samuel Thibault <samuel.thibault@ens-lyon.org>
40 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
41 * Winbond W83759A, Promise PDC20230-B
127 enum controller { enum
140 UNKNOWN = -1
144 unsigned long timing; member
148 enum controller type;
[all …]
H A Dpata_artop.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_artop.c - ARTOP ATA controller driver
9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
11 * driver by Thibaut VARENE <varenet@parisc-linux.org>
34 * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
43 * artop62x0_pre_reset - probe begin
57 struct ata_port *ap = link->ap; in artop62x0_pre_reset()
58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in artop62x0_pre_reset()
61 if ((pdev->device & 1) && in artop62x0_pre_reset()
62 !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no])) in artop62x0_pre_reset()
[all …]
H A Dpata_it821x.c2 * pata_it821x.c - IT821x PATA for new ATA layer
22 * The ITE8212 isn't exactly a standard IDE controller. It has two
23 * modes. In pass through mode then it is an IDE controller. In its smart
24 * mode its actually quite a capable hardware raid controller disguised
25 * as an IDE controller. Smart mode only understands DMA read/write and
36 * raid then the controller firmware dies
41 * - In pass through mode we do all the work you would expect
42 * - In smart mode the clocking set up is done by the controller generally
44 * - There are a few extra vendor commands that actually talk to the
45 * controller but only work PIO with no IRQ.
[all …]
H A Dpata_oldpiix.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_oldpiix.c - Intel PATA/SATA controllers
10 * SITRE and the slave timing registers. This means that you have to
11 * set timing per channel, or be clever. Libata tells us whenever it
31 * oldpiix_pre_reset - probe begin
40 struct ata_port *ap = link->ap; in oldpiix_pre_reset()
41 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in oldpiix_pre_reset()
47 if (!pci_test_config_bits(pdev, &oldpiix_enable_bits[ap->port_no])) in oldpiix_pre_reset()
48 return -ENOENT; in oldpiix_pre_reset()
54 * oldpiix_set_piomode - Initialize host controller PATA PIO timings
[all …]
H A Dpata_ns87415.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_ns87415.c - NS87415 (and PARISC SUPERIO 87560) PATA
7 * This is a fairly generic MWDMA controller. It has some limitations
8 * as it requires timing reloads on PIO/DMA transitions but it is otherwise
15 * The same cell appears in the 87560 controller used by some PARISC
21 * 8bit shared timing.
39 * ns87415_set_mode - Initialize host controller mode timings
44 * Program the mode registers for this controller, channel and
54 struct pci_dev *dev = to_pci_dev(ap->host->dev); in ns87415_set_mode()
55 int unit = 2 * ap->port_no + adev->devno; in ns87415_set_mode()
[all …]
H A Dpata_it8213.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_it8213.c - iTE Tech. Inc. IT8213 PATA driver
5 * The IT8213 is a very Intel ICH like device for timing purposes, having
25 * it8213_pre_reset - probe begin
38 struct ata_port *ap = link->ap; in it8213_pre_reset()
39 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in it8213_pre_reset()
40 if (!pci_test_config_bits(pdev, &it8213_enable_bits[ap->port_no])) in it8213_pre_reset()
41 return -ENOENT; in it8213_pre_reset()
47 * it8213_cable_detect - check for 40/80 pin
56 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in it8213_cable_detect()
[all …]
H A Dpata_efar.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_efar.c - EFAR PIIX clone controller driver
6 * (C) 2009-2010 Bartlomiej Zolnierkiewicz
29 * efar_pre_reset - Enable bits
43 struct ata_port *ap = link->ap; in efar_pre_reset()
44 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in efar_pre_reset()
46 if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no])) in efar_pre_reset()
47 return -ENOENT; in efar_pre_reset()
53 * efar_cable_detect - check for 40/80 pin
62 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in efar_cable_detect()
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI AM654 MMC Controller
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
[all …]
H A Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - microchip,pic64gx-sd4hc
19 - mobileye,eyeq-sd4hc
[all …]
/linux/Documentation/devicetree/bindings/media/xilinx/
H A Dxlnx,v-tc.txt1 Xilinx Video Timing Controller (VTC)
2 ------------------------------------
4 The Video Timing Controller is a general purpose video timing generator and
9 - compatible: Must be "xlnx,v-tc-6.1".
11 - reg: Physical base address and length of the registers set for the device.
13 - clocks: Must contain a clock specifier for the VTC core and timing
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
28 compatible = "xlnx,v-tc-6.1";
/linux/drivers/mtd/nand/raw/
H A Ddenali.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * NAND Flash Controller Device Driver
4 * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
295 * struct denali_chip_sel - per-CS data of Denali NAND
297 * @bank: bank id of the controller this CS is connected to
298 * @hwhr2_and_we_2_re: value of timing register HWHR2_AND_WE_2_RE
299 * @tcwaw_and_addr_2_data: value of timing register TCWAW_AND_ADDR_2_DATA
300 * @re_2_we: value of timing register RE_2_WE
301 * @acc_clks: value of timing register ACC_CLKS
302 * @rdwr_en_lo_cnt: value of timing register RDWR_EN_LO_CNT
[all …]
/linux/Documentation/driver-api/memory-devices/
H A Dti-gpmc.rst1 .. SPDX-License-Identifier: GPL-2.0
4 GPMC (General Purpose Memory Controller)
7 GPMC is an unified memory controller dedicated to interfacing external
14 * Pseudo-SRAM devices
20 GPMC generic timing calculation:
29 generic timing routine was developed to achieve above requirements.
37 happen that timing as specified by peripheral datasheet is not present
38 in timing structure, in this scenario, try to correlate peripheral
39 timing to the one available. If that doesn't work, try to add a new
40 field as required by peripheral, educate generic timing routine to
[all …]
/linux/Documentation/devicetree/bindings/ata/
H A Dceva,ahci-1v84.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ceva AHCI SATA Controller
10 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
13 The Ceva SATA controller mostly conforms to the AHCI interface with some
14 special extensions to add functionality, is a high-performance dual-port
15 SATA host controller with an AHCI compliant command layer which supports
21 const: ceva,ahci-1v84
[all …]
/linux/drivers/memory/tegra/
H A Dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/dma-mapping.h>
18 #include <linux/tegra-icc.h>
26 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
29 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
32 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
35 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
38 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
41 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
[all …]
H A Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
15 #include <linux/interconnect-provider.h>
512 /* protect shared rate-change code path */
516 /* Timing change sequence functions */
521 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
522 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
530 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
533 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
539 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
[all …]
/linux/Documentation/devicetree/bindings/display/panel/
H A Dpanel-mipi-dbi-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Noralf Trønnes <noralf@tronnes.org>
13 This binding is for display panels using a MIPI DBI compatible controller
23 - Power:
24 - Vdd: Power supply for display module
25 Called power-supply in this binding.
26 - Vddi: Logic level supply for interface signals
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dfsl,imx-weim.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
16 wireless and mobile applications that use low-power technology. The actual
21 pattern: "^memory-controller@[0-9a-f]+$"
25 - enum:
26 - fsl,imx1-weim
[all …]
/linux/include/uapi/linux/can/
H A Dnetlink.h1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
25 * CAN bit-timing parameters
27 * For further information, please read chapter "8 BIT TIMING
32 __u32 bitrate; /* Bit-rat
[all...]
/linux/Documentation/gpu/
H A Dkomeda-kms.rst1 .. SPDX-License-Identifier: GPL-2.0
23 -----
30 ------
39 -------------------
47 --------------------------
52 -----------------------------
56 Timing controller (timing_ctrlr)
57 --------------------------------
58 Final stage of display pipeline, Timing controller is not for the pixel
59 handling, but only for controlling the display timing.
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
16 two memory channels. The Tegra124 Memory Controller handles memory requests
22 const: nvidia,tegra124-mc
[all …]
H A Dnvidia,tegra30-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra30 SoC Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 Tegra30 Memory Controller architecturally consists of the following parts:
33 The Tegra30 Memory Controller handles memory requests from internal clients
[all …]
/linux/drivers/clk/tegra/
H A Dclk-tegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
48 * When we change the timing to a timing with a parent that has the same
50 * timing that has a different clock source.
105 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
120 struct emc_timing *timing = NULL; in emc_determine_rate() local
125 for (k = 0; k < tegra->num_timings; k++) { in emc_determine_rate()
126 if (tegra->timings[k].ram_code == ram_code) in emc_determine_rate()
130 for (t = k; t < tegra->num_timings; t++) { in emc_determine_rate()
[all …]
/linux/drivers/staging/sm750fb/
H A Dddk750_display.c1 // SPDX-License-Identifier: GPL-2.0
9 /* state != 0 means turn on both timing & plane en_bit */ in set_display_control()
24 * Timing should be enabled first before enabling the in set_display_control()
52 * before modifying the timing enable bit. in set_display_control()
74 while (delay-- > 0) { in primary_wait_vertical_sync()
118 /* set panel path controller select */ in ddk750_set_logical_disp_out()
127 /* set crt path controller select */ in ddk750_set_logical_disp_out()
138 /* set primary timing and plane en_bit */ in ddk750_set_logical_disp_out()
143 /* set secondary timing and plane en_bit*/ in ddk750_set_logical_disp_out()
/linux/drivers/nvmem/
H A Dimx-ocotp.c1 // SPDX-License-Identifier: GPL-2.0-only
14 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
21 #include <linux/nvmem-provider.h>
107 void __iomem *base = priv->base; in imx_ocotp_wait_for_busy()
109 bm_ctrl_busy = priv->params->ctrl.bm_busy; in imx_ocotp_wait_for_busy()
110 bm_ctrl_error = priv->params->ctrl.bm_error; in imx_ocotp_wait_for_busy()
114 for (count = 10000; count >= 0; count--) { in imx_ocotp_wait_for_busy()
124 * - A write is performed to a shadow register during a shadow in imx_ocotp_wait_for_busy()
128 * - A write is performed to a shadow register which has been in imx_ocotp_wait_for_busy()
130 * - A read is performed to from a shadow register which has in imx_ocotp_wait_for_busy()
[all …]

12345678910>>...20