Lines Matching +full:timing +full:- +full:controller

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * NAND Flash Controller Device Driver
4  * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
295  * struct denali_chip_sel - per-CS data of Denali NAND
297  * @bank:                  bank id of the controller this CS is connected to
298  * @hwhr2_and_we_2_re:     value of timing register HWHR2_AND_WE_2_RE
299  * @tcwaw_and_addr_2_data: value of timing register TCWAW_AND_ADDR_2_DATA
300  * @re_2_we:               value of timing register RE_2_WE
301  * @acc_clks:              value of timing register ACC_CLKS
302  * @rdwr_en_lo_cnt:        value of timing register RDWR_EN_LO_CNT
303  * @rdwr_en_hi_cnt:        value of timing register RDWR_EN_HI_CNT
304  * @cs_setup_cnt:          value of timing register CS_SETUP_CNT
305  * @re_2_re:               value of timing register RE_2_RE
320  * struct denali_chip - per-chip data of Denali NAND
323  * @node:  node to be used to associate this chip with the controller
325  * @sels:  the array of per-cs data
335  * struct denali_controller - Denali NAND controller data
337  * @controller:     base NAND controller structure
339  * @chips:          the list of chips attached to this controller
346  * @irq_mask:       interrupt bits the controller is waiting for
353  * @nbanks:         the number of banks supported by this controller
355  * @caps:           controller capabilities that cannot be detected run-time
362 	struct nand_controller controller;  member