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Searched +full:timing +full:- +full:adjustment (Results 1 – 25 of 73) sorted by relevance

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/linux/drivers/gpu/drm/sti/
H A Dsti_awg_utils.c1 // SPDX-License-Identifier: GPL-2.0
11 #define AWG_DELAY (-5)
48 if (fwparams->instruction_offset >= AWG_MAX_INST) { in awg_generate_instr()
50 return -EINVAL; in awg_generate_instr()
57 arg--; /* pixel adjustment */ in awg_generate_instr()
58 arg_tmp--; in awg_generate_instr()
105 return -EINVAL; in awg_generate_instr()
108 arg_tmp = arg_tmp - arg; in awg_generate_instr()
113 fwparams->ram_code[fwparams->instruction_offset] = in awg_generate_instr()
115 fwparams->instruction_offset++; in awg_generate_instr()
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/linux/Documentation/devicetree/bindings/sound/
H A Dst,sta350.txt7 - compatible: "st,sta350"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - vdd-dig-supply: regulator spec, providing 3.3V
17 - vdd-pll-supply: regulator spec, providing 3.3V
18 - vcc-supply: regulator spec, providing 5V - 26V
22 - st,output-conf: number, Selects the output configuration:
23 0: 2-channel (full-bridge) power, 2-channel data-out
24 1: 2 (half-bridge). 1 (full-bridge) on-board power
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/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_10nm.c2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
15 * DSI PLL 10nm - clock diagram (eg: DSI0):
20 * +---------+ | +----------+ | +----+
21 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22 * +---------+ | +----------+ | +----+
26 * | | +----+ | |\ dsi0_pclk_mux
27 * | |--| /2 |--o--| \ |
28 * | | +----+ | \ | +---------+
29 …* | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_…
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/linux/drivers/video/backlight/
H A Dtdo24m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * tdo24m - SPI-based drivers for Toppoly TDO24M series LCD panels
44 #define CMD_NULL (-1)
91 CMD1(0xd1, 0x01), /* CKV timing control on/off */
92 CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
93 CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
94 CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
95 CMD1(0xd5, 0x14), /* ASW timing control (2) */
104 CMD1(0xd8, 0x01), /* CKV timing control on/off */
105 CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
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/linux/drivers/mmc/host/
H A Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
17 #include "sdhci-pltfm.h"
18 #include "sdhci-xenon.h"
87 * according to board actual timing.
120 /* Offset of Timing Adjust register */
130 /* Offset of Logic Timing Adjust register */
134 /* value in Logic Timing Adjustment register */
209 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); in xenon_alloc_emmc_phy()
211 return -ENOMEM; in xenon_alloc_emmc_phy()
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H A Drenesas_sdhi_core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
13 * Copyright 2004-2005 Phil Blundell
14 * Copyright 2007-2008 OpenedHand Ltd.
27 #include <linux/mmc/slot-gpio.h>
30 #include <linux/pinctrl/pinctrl-state.h>
95 struct mmc_host *mmc = host->mmc; in renesas_sdhi_clk_enable()
99 ret = clk_prepare_enable(priv->clk_cd); in renesas_sdhi_clk_enable()
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/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8m2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
19 /delete-node/ video-lut@20;
21 canvas: video-lut@48 {
22 compatible = "amlogic,meson8m2-canvas", "amlogic,canvas";
28 compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
35 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
37 reset-names = "stmmaceth";
41 compatible = "amlogic,meson8m2-aobus-pinctrl",
42 "amlogic,meson8-aobus-pinctrl";
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/linux/drivers/gpu/drm/amd/display/dc/spl/
H A Ddc_spl.c1 // SPDX-License-Identifier: MIT
52 int r0_x_end = r0->x + r0->width; in intersect_rec()
53 int r1_x_end = r1->x + r1->width; in intersect_rec()
54 int r0_y_end = r0->y + r0->height; in intersect_rec()
55 int r1_y_end = r1->y + r1->height; in intersect_rec()
57 rec.x = r0->x > r1->x ? r0->x : r1->x; in intersect_rec()
58 rec.width = r0_x_end > r1_x_end ? r1_x_end - rec.x : r0_x_end - rec.x; in intersect_rec()
59 rec.y = r0->y > r1->y ? r0->y : r1->y; in intersect_rec()
60 rec.height = r0_y_end > r1_y_end ? r1_y_end - rec.y : r0_y_end - rec.y; in intersect_rec()
85 * desktop to a 2560x1440 timing with a plane rect in the middle in calculate_plane_rec_in_timing_active()
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/linux/drivers/net/wireless/intel/iwlegacy/
H A D4965.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
15 #include <linux/dma-mapping.h>
29 * il_verify_inst_sparse - verify runtime uCode image in card vs. host,
44 /* read data comes through single port, auto-incr addr */ in il4965_verify_inst_sparse()
50 ret = -EIO; in il4965_verify_inst_sparse()
61 * il4965_verify_inst_full - verify runtime uCode image in card vs. host,
77 for (; len > 0; len -= sizeof(u32), image++) { in il4965_verify_inst_full()
78 /* read data comes through single port, auto-incr addr */ in il4965_verify_inst_full()
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/linux/drivers/clocksource/
H A Dtimer-cadence-ttc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2013 Xilinx
23 * This driver configures the 2 16/32-bit count-up timers as follows:
30 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
34 * obtained from device tree. The pre-scaler of 32 is used.
55 * Setup the timers to use pre-scaling, using a fixed value for now that will
60 #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
67 * struct ttc_timer - This definition defines local timer structure
105 * ttc_set_interval - Set the timer interval value
115 /* Disable the counter, set the counter value and re-enable counter */ in ttc_set_interval()
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/linux/drivers/media/i2c/
H A Dks0127.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * for the Matrox Marvel G200,G400 and Rainbow Runner-G series
20 * V1.1 Gerard v.d. Horst Added some debugoutput, reset the video-standard
31 #include <media/v4l2-device.h>
250 table[KS_UVOFFH] = 0x00; /* UV Offset Adjustment High */ in init_reg_defaults()
251 table[KS_UVOFFL] = 0x00; /* UV Offset Adjustment Low */ in init_reg_defaults()
252 table[KS_UGAIN] = 0x00; /* U Component Gain Adjustment */ in init_reg_defaults()
253 table[KS_VGAIN] = 0x00; /* V Component Gain Adjustment */ in init_reg_defaults()
257 table[KS_POLCTL] = 0x41; /* Timing Signal Polarity Control */ in init_reg_defaults()
273 /* Command Register F, update -immediately- */ in init_reg_defaults()
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/linux/kernel/time/
H A Dclocksource.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include "tick-internal.h"
27 u64 delta = clocksource_delta(end, start, cs->mask, cs->max_raw_delta); in cycles_to_nsec_safe()
29 if (likely(delta < cs->max_cycles)) in cycles_to_nsec_safe()
30 return clocksource_cyc2ns(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
32 return mul_u64_u32_shr(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
36 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
71 sftacc--; in clocks_calc_mult_shift()
78 for (sft = 32; sft > 0; sft--) { in clocks_calc_mult_shift()
90 /*[Clocksource internal variables]---------
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/linux/drivers/net/wireless/intel/iwlwifi/dvm/
H A Drxon.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
9 #include "iwl-trans.h"
10 #include "iwl-modparams.h"
21 memset(&ctx->staging, 0, sizeof(ctx->staging)); in iwl_connection_init_rx_config()
23 if (!ctx->vif) { in iwl_connection_init_rx_config()
24 ctx->staging.dev_type = ctx->unused_devtype; in iwl_connection_init_rx_config()
26 switch (ctx->vif->type) { in iwl_connection_init_rx_config()
28 ctx->staging.dev_type = ctx->ap_devtype; in iwl_connection_init_rx_config()
32 ctx->staging.dev_type = ctx->station_devtype; in iwl_connection_init_rx_config()
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/linux/drivers/gpu/drm/radeon/
H A Dradeon_legacy_tv.c1 // SPDX-License-Identifier: MIT
16 #define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on t…
17 #define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */
25 * Indexes in h. code timing table for horizontal line position adjustment
33 #define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */
172 { /* NTSC timing for 27 Mhz ref clk */
187 { /* PAL timing for 27 Mhz ref clk */
202 { /* NTSC timing for 14 Mhz ref clk */
217 { /* PAL timing for 14 Mhz ref clk */
239 struct drm_device *dev = radeon_encoder->base.dev; in radeon_legacy_tv_get_std_mode()
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
60 * (access to non-DC registers will hang FPGA) */
145 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
147 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
219 /* native display timing*/
224 *_not_ related to the Reduced Blanking adjustment*/
232 /* this timing should be used only in tiled mode*/
237 Must be zero for wired displays and non-zero for
275 /* these timing might not work, least important*/
330 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
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/linux/Documentation/virt/kvm/x86/
H A Dtimekeeping.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
13 2) Timing Devices
21 the virtualization of this platform is the plethora of timing devices available
32 information relevant to KVM and hardware-based virtualization.
34 2. Timing Devices
41 2.1. i8254 - PIT
42 ----------------
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
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/linux/drivers/media/platform/renesas/rzg2l-cru/
H A Drzg2l-csi2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Renesas RZ/G2L MIPI CSI-2 Receiver
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-fwnode.h>
24 #include <media/v4l2-mc.h>
25 #include <media/v4l2-subdev.h>
60 /* D-PHY Control Register 0 */
65 /* D-PHY Timing Register 0 */
70 /* D-PHY Timing Register 1 */
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
90 * relatively the same independent from timing used.
95 dc->ctx->logger
100 #define UNABLE_TO_SPLIT -1
230 init_data->num_virtual_links, dc); in dc_create_resource_pool()
234 init_data->num_virtual_links, dc); in dc_create_resource_pool()
238 init_data->num_virtual_links, dc); in dc_create_resource_pool()
243 init_data->num_virtual_links, dc); in dc_create_resource_pool()
247 init_data->num_virtual_links, dc); in dc_create_resource_pool()
251 init_data->num_virtual_links, dc); in dc_create_resource_pool()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_vblank.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2022-2023 Intel Corporation
18 * This timing diagram depicts the video signal in and
34 * | may be shifted forward 1-3 extra lines via TRANSCONF
41 * ----va---> <-----------------vb--------------------> <--------va-------------
42 * | | <----vs-----> |
43 …* -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter …
44 …* -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter …
45 …* -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter …
60 * - most events happen at the start of horizontal sync
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/linux/drivers/rtc/
H A Drtc-amlogic-a4.c1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
9 #include <linux/clk-provider.h>
30 #define RTC_SEC_ADJUST_REG (0x6 << 2) /* Control second-based timing adjustment */
105 if (!rtc->rtc_enabled) in aml_rtc_read_time()
106 return -EINVAL; in aml_rtc_read_time()
108 regmap_read(rtc->map, RTC_REAL_TIME, &time_sec); in aml_rtc_read_time()
109 if (rtc->config->gray_stored) in aml_rtc_read_time()
123 if (!rtc->rtc_enabled) { in aml_rtc_set_time()
124 regmap_write_bits(rtc->map, RTC_CTRL, RTC_ENABLE, RTC_ENABLE); in aml_rtc_set_time()
126 rtc->rtc_enabled = regmap_test_bits(rtc->map, RTC_CTRL, RTC_ENABLE); in aml_rtc_set_time()
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/linux/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
14 #include "tegra210-emc.h"
15 #include "tegra210-mc.h"
36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__)
53 * PTFV defines - basically just indexes into the per table PTFV array.
78 ({ next->ptfv_list[(dev)] = \
79 next->ptfv_list[(dev)] / \
80 next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; })
86 ({ next->ptfv_list[(dev)] += \
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/linux/drivers/net/can/ctucanfd/
H A Dctucanfd_base.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
7 * Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded
8 * Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
9 * Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
49 * - when a buffer transitions to empty state, rotate order and priorities
50 * - if more buffers seem to transition at the same time, rotate by the number of buffers
51 * - it may be assumed that buffers transition to empty state in FIFO order (because we manage
53 * - at frame filling, do not rotate anything, just increment buffer modulo counter
114 iowrite32(val, priv->mem_base + reg); in ctucan_write32_le()
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/linux/drivers/gpu/drm/
H A Ddrm_modes.c2 * Copyright © 1997-2003 by The XFree86 Project, Inc.
4 * Copyright © 2007-2008 Intel Corporation
6 * Copyright 2005-2006 Luc Verhaegen
53 * drm_mode_debug_printmodeline - print a mode to dmesg
65 * drm_mode_create - create a new display mode
87 * drm_mode_destroy - remove a mode
103 * drm_mode_probed_add - add a mode to a connector's probed_mode list
114 WARN_ON(!mutex_is_locked(&connector->dev->mode_config.mutex)); in drm_mode_probed_add()
116 list_add_tail(&mode->head, &connector->probed_modes); in drm_mode_probed_add()
127 * - https://web.archive.org/web/20220406232708/http://www.kolumbus.fi/pami1/video/pal_ntsc.html
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/linux/Documentation/networking/device_drivers/hamradio/
H A Dz8530drv.rst1 .. SPDX-License-Identifier: GPL-2.0
5 SCC.C - Linux driver for Z8530 based HDLC cards for AX.25
14 1. ftp://ftp.ccac.rwth-aachen.de/pub/jr/z8530drv-utils_3.0-3.tar.gz
16 2. ftp://ftp.pspt.fi/pub/ham/linux/ax25/z8530drv-utils_3.0-3.tar.gz
41 AX.25-HOWTO on how to emulate a KISS TNC on network device drivers.
54 please read 'man insmod' that comes with module-init-tools.
64 of your rc.*-files. This has to be done BEFORE you can
92 - this is just a delimiter to make sccinit a bit simpler to
96 - the address of the data port A of this Z8530 (needed)
98 - the address of the control port A (needed)
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/linux/drivers/media/usb/gspca/
H A Dspca501.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * V4L2 by Jean-Francois Moine <http://moinejf.free.fr>
120 /* Color correction and RGB-to-YUV transformation coefficients changing */
154 {0x0, 0xe4, 0x04}, /* DCLK*2 clock phase adjustment */
155 {0x0, 0x08, 0x05}, /* ADCK phase adjustment, inv. ext. VB */
156 {0x0, 0x03, 0x06}, /* FR phase adjustment */
157 {0x0, 0x01, 0x07}, /* FCDS phase adjustment */
158 {0x0, 0x39, 0x08}, /* FS phase adjustment */
159 {0x0, 0x88, 0x0a}, /* FH1 phase and delay adjustment */
483 /* Strange - looks like the 501 driver doesn't do anything
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