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/linux/drivers/gpu/drm/tegra/
H A Dmipi-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "mipi-phy.h"
12 * Default D-PHY timings based on MIPI D-PHY specification. Derived from the
13 * valid ranges specified in Section 6.9, Table 14, Page 40 of the D-PHY
16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
[all …]
/linux/drivers/clk/tegra/
H A Dclk-tegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
48 * When we change the timing to a timing with a parent that has the same
50 * timing that has a different clock source.
105 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
120 struct emc_timing *timing = NULL; in emc_determine_rate() local
125 for (k = 0; k < tegra->num_timings; k++) { in emc_determine_rate()
126 if (tegra->timings[k].ram_code == ram_code) in emc_determine_rate()
130 for (t = k; t < tegra->num_timings; t++) { in emc_determine_rate()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dtiming.c26 #include <subdev/bios/timing.h>
33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
51 return timing; in nvbios_timingTe()
[all …]
/linux/drivers/video/fbdev/
H A Dgbefb.c4 * Copyright (C) 1999 Silicon Graphics, Inc. - Jeffrey Newquist
5 * Copyright (C) 2002 Vivien Chappelier <vivien.chappelier@linux-mips.org>
14 #include <linux/dma-mapping.h>
15 #include <linux/dma-direct.h>
38 struct gbe_timing_info timing; member
45 /* macro for fastest write-though access to the framebuffer */
64 #define TILE_MASK (TILE_SIZE - 1)
88 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
103 .height = -1,
104 .width = -1,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/
H A Ddcn201_optc.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
32 optc1->tg_regs->reg
35 optc1->base.ctx
39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
46 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); in optc201_triplebuffer_lock()
70 const struct dc_crtc_timing *timing) in optc201_validate_timing() argument
77 ASSERT(timing != NULL); in optc201_validate_timing()
79 v_blank = (timing->v_total - timing->v_addressable - in optc201_validate_timing()
80 timing->v_border_top - timing->v_border_bottom); in optc201_validate_timing()
82 h_blank = (timing->h_total - timing->h_addressable - in optc201_validate_timing()
[all …]
/linux/drivers/video/fbdev/via/
H A Dvia_modesetting.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
12 #include <linux/via-core.h>
18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
[all …]
/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_20nm.c1 // SPDX-License-Identifier: GPL-2.0-only
11 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
13 void __iomem *base = phy->base; in dsi_20nm_dphy_set_timing()
15 writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_20nm_dphy_set_timing()
17 writel(DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail), in dsi_20nm_dphy_set_timing()
19 writel(DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare), in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
24 writel(DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit), in dsi_20nm_dphy_set_timing()
26 writel(DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero), in dsi_20nm_dphy_set_timing()
28 writel(DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare), in dsi_20nm_dphy_set_timing()
[all …]
/linux/drivers/gpu/drm/sti/
H A Dsti_awg_utils.c1 // SPDX-License-Identifier: GPL-2.0
11 #define AWG_DELAY (-5)
48 if (fwparams->instruction_offset >= AWG_MAX_INST) { in awg_generate_instr()
50 return -EINVAL; in awg_generate_instr()
57 arg--; /* pixel adjustment */ in awg_generate_instr()
58 arg_tmp--; in awg_generate_instr()
105 return -EINVAL; in awg_generate_instr()
108 arg_tmp = arg_tmp - arg; in awg_generate_instr()
113 fwparams->ram_code[fwparams->instruction_offset] = in awg_generate_instr()
115 fwparams->instruction_offset++; in awg_generate_instr()
[all …]
/linux/drivers/media/rc/img-ir/
H A Dimg-ir-hw.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright 2010-2014 Imagination Technologies Ltd.
12 #include <media/rc-core.h>
18 #define IMG_IR_CODETYPE_BIPHASE 0x2 /* RC-5/6 */
19 #define IMG_IR_CODETYPE_2BITPULSEPOS 0x3 /* RC-MM */
22 /* Timing information */
25 * struct img_ir_control - Decoder control settings
53 * struct img_ir_timing_range - range of timing values
54 * @min: Minimum timing value
55 * @max: Maximum timing value (if < @min, this will be set to @min during
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramnv50.c34 #include <subdev/bios/timing.h>
71 #define T(t) cfg->timing_10_##t
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
75 struct nvbios_ramcfg *cfg = &ram->base.target.bios; in nv50_ram_timing_calc()
76 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in nv50_ram_timing_calc()
77 struct nvkm_device *device = subdev->device; in nv50_ram_timing_calc()
86 switch ((!T(CWL)) * ram->base.type) { in nv50_ram_timing_calc()
88 T(CWL) = T(CL) - 1; in nv50_ram_timing_calc()
96 if (device->chipset == 0xa0) { in nv50_ram_timing_calc()
97 unkt3b = 0x19 + ram->base.next->bios.rammap_00_16_40; in nv50_ram_timing_calc()
[all …]
/linux/drivers/ata/
H A Dpata_triflex.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_triflex.c - Compaq PATA for new ATA layer
15 * Copyright (C) 2002 Hewlett-Packard Development Group, L.P.
36 * triflex_prereset - probe begin
50 struct ata_port *ap = link->ap; in triflex_prereset()
51 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in triflex_prereset()
53 if (!pci_test_config_bits(pdev, &triflex_enable_bits[ap->port_no])) in triflex_prereset()
54 return -ENOENT; in triflex_prereset()
62 * triflex_load_timing - timing configuration
75 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in triflex_load_timing()
[all …]
H A Dpata_cs5530.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata-cs5530.c - CS5530 PATA for new ATA layer
28 unsigned long bmdma = (unsigned long)ap->ioaddr.bmdma_addr; in cs5530_port_base()
30 return (void __iomem *)((bmdma & ~0x0F) + 0x20 + 0x10 * ap->port_no); in cs5530_port_base()
34 * cs5530_set_piomode - PIO setup
56 /* Now load the right timing register */ in cs5530_set_piomode()
57 if (adev->devno) in cs5530_set_piomode()
60 iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base); in cs5530_set_piomode()
64 * cs5530_set_dmamode - DMA timing setup
76 u32 tuning, timing = 0; in cs5530_set_dmamode() local
[all …]
/linux/Documentation/driver-api/memory-devices/
H A Dti-gpmc.rst1 .. SPDX-License-Identifier: GPL-2.0
14 * Pseudo-SRAM devices
20 GPMC generic timing calculation:
29 generic timing routine was developed to achieve above requirements.
37 happen that timing as specified by peripheral datasheet is not present
38 in timing structure, in this scenario, try to correlate peripheral
39 timing to the one available. If that doesn't work, try to add a new
40 field as required by peripheral, educate generic timing routine to
45 Generic timing routine has been verified to work properly on
48 A word of caution: generic timing routine has been developed based
[all …]
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/tests/
H A Damdgpu_dm_connector_test.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
36 * dm_test_subconnector_type_none - Test Subconnector type none
45 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; in dm_test_subconnector_type_none()
50 * dm_test_subconnector_type_vga - Test Subconnector type vga
59 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER; in dm_test_subconnector_type_vga()
64 * dm_test_subconnector_type_dvi_converter - Test Subconnector type dvi converter
73 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER; in dm_test_subconnector_type_dvi_converter()
78 * dm_test_subconnector_type_dvi_dongle - Tes
230 struct dc_crtc_timing timing = {}; dm_test_adjust_colour_depth_fits_at_888() local
249 struct dc_crtc_timing timing = {}; dm_test_adjust_colour_depth_reduces_to_888() local
269 struct dc_crtc_timing timing = {}; dm_test_adjust_colour_depth_10bpc_passes() local
288 struct dc_crtc_timing timing = {}; dm_test_adjust_colour_depth_420_halves_clk() local
308 struct dc_crtc_timing timing = {}; dm_test_adjust_colour_depth_420_reduces() local
333 struct dc_crtc_timing timing = {}; dm_test_adjust_colour_depth_reduces_12bpc_to_10bpc() local
352 struct dc_crtc_timing timing = {}; dm_test_adjust_colour_depth_16bpc_no_fallback() local
372 struct dc_crtc_timing timing = {}; dm_test_adjust_colour_depth_none_fits() local
390 struct dc_crtc_timing timing = {}; dm_test_adjust_colour_depth_invalid_depth() local
410 struct dc_crtc_timing timing = {}; dm_test_output_color_space_default_rgb_full() local
427 struct dc_crtc_timing timing = {}; dm_test_output_color_space_default_rgb_limited() local
444 struct dc_crtc_timing timing = {}; dm_test_output_color_space_default_ycbcr709() local
463 struct dc_crtc_timing timing = {}; dm_test_output_color_space_default_ycbcr601_limited() local
481 struct dc_crtc_timing timing = {}; dm_test_output_color_space_bt601_y_only() local
497 struct dc_crtc_timing timing = {}; dm_test_output_color_space_bt601() local
513 struct dc_crtc_timing timing = {}; dm_test_output_color_space_bt709() local
529 struct dc_crtc_timing timing = {}; dm_test_output_color_space_bt709_y_only() local
545 struct dc_crtc_timing timing = {}; dm_test_output_color_space_oprgb() local
560 struct dc_crtc_timing timing = {}; dm_test_output_color_space_bt2020_rgb() local
576 struct dc_crtc_timing timing = {}; dm_test_output_color_space_bt2020_rgb_limited() local
593 struct dc_crtc_timing timing = {}; dm_test_output_color_space_bt2020_ycc() local
610 struct dc_crtc_timing timing = {}; dm_test_output_color_space_default_ycbcr709_y_only() local
629 struct dc_crtc_timing timing = {}; dm_test_output_color_space_default_ycbcr601() local
648 struct dc_crtc_timing timing = {}; dm_test_output_color_space_bt2020_ycc_rgb_encoding() local
665 struct dc_crtc_timing timing = {}; dm_test_output_color_space_bt2020_ycc_rgb_encoding_limited() local
683 struct dc_crtc_timing timing = {}; dm_test_output_color_space_bt2020_rgb_ycc_encoding() local
3445 struct dc_crtc_timing *timing = &ctx->stream->timing; dm_test_fill_stream_borders_zeroed() local
3473 struct dc_crtc_timing *timing = &ctx->stream->timing; dm_test_fill_stream_rgb_defaults() local
3498 struct dc_crtc_timing *timing = &ctx->stream->timing; dm_test_fill_stream_sync_polarity_positive() local
3517 struct dc_crtc_timing *timing = &ctx->stream->timing; dm_test_fill_stream_sync_polarity_negative() local
3540 struct dc_crtc_timing *timing = &ctx->stream->timing; dm_test_fill_stream_inherits_old_stream() local
3571 struct dc_crtc_timing *timing = &ctx->stream->timing; dm_test_fill_stream_timing_from_crtc() local
3607 struct dc_crtc_timing *timing = &ctx->stream->timing; dm_test_fill_stream_color_depth_requested_bpc() local
3644 struct dc_crtc_timing *timing = &ctx->stream->timing; dm_test_fill_stream_aspect_ratio() local
3667 struct dc_crtc_timing *timing = &ctx->stream->timing; dm_test_fill_stream_encoding_from_caller_ycbcr420() local
3686 struct dc_crtc_timing *timing = &ctx->stream->timing; dm_test_fill_stream_encoding_from_caller_ycbcr422() local
3705 struct dc_crtc_timing *timing = &ctx->stream->timing; dm_test_fill_stream_encoding_from_caller_ycbcr444() local
3725 struct dc_crtc_timing *timing = &ctx->stream->timing; dm_test_fill_stream_hdmi_ep_clamps_depth() local
3750 struct dc_crtc_timing *timing = &ctx->stream->timing; dm_test_fill_stream_non_hdmi_ep_keeps_depth() local
[all...]
/linux/Documentation/devicetree/bindings/mips/cavium/
H A Dbootbus.txt7 - compatible: "cavium,octeon-3860-bootbus"
11 - reg: The base address of the Boot Bus' register bank.
13 - #address-cells: Must be <2>. The first cell is the chip select
16 - #size-cells: Must be <1>.
18 - ranges: There must be one one triplet of (child-bus-address,
19 parent-bus-address, length) for each active chip select. If the
27 - compatible: "cavium,octeon-3860-bootbus-config"
29 - cavium,cs-index: A single cell indicating the chip select that
32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
34 - cavium,t-ce: A cell specifying the CE timing (in nS).
[all …]
/linux/Documentation/devicetree/bindings/media/xilinx/
H A Dxlnx,v-tc.txt1 Xilinx Video Timing Controller (VTC)
2 ------------------------------------
4 The Video Timing Controller is a general purpose video timing generator and
9 - compatible: Must be "xlnx,v-tc-6.1".
11 - reg: Physical base address and length of the registers set for the device.
13 - clocks: Must contain a clock specifier for the VTC core and timing
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
28 compatible = "xlnx,v-tc-6.1";
/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
45 /* Trigger Source Select - ASIC-defendant, actual values for the
74 /* Trigger Source Select - ASIC-dependant, actual values for the
126 /* determine if given timing can be supported by TG */
129 const struct dc_crtc_timing *timing,
134 /* Program timing generator with given timing */
139 /* Disable/Enable Timing Generator */
166 /*********** Timing Generator Synchronization routines ****/
188 /* disabling trigger-reset */
200 /* Fully program CRTC timing in timing generator */
[all …]
/linux/arch/arm/mach-pxa/
H A Dsmemc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
21 #define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
24 #define MCMEM0 (SMEMC_VIRT + 0x28) /* Card interface Common Memory Space Socket 0 Timing */
25 #define MCMEM1 (SMEMC_VIRT + 0x2C) /* Card interface Common Memory Space Socket 1 Timing */
26 #define MCATT0 (SMEMC_VIRT + 0x30) /* Card interface Attribute Space Socket 0 Timing Configuratio…
27 #define MCATT1 (SMEMC_VIRT + 0x34) /* Card interface Attribute Space Socket 1 Timing Configuratio…
28 #define MCIO0 (SMEMC_VIRT + 0x38) /* Card interface I/O Space Socket 0 Timing Configuration */
29 #define MCIO1 (SMEMC_VIRT + 0x3C) /* Card interface I/O Space Socket 1 Timing Configuration */
31 #define BOOT_DEF (SMEMC_VIRT + 0x44) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SE…
44 …e MCMEM(s) (SMEMC_VIRT + 0x28 + ((s)<<2)) /* Card interface Common Memory Space Socket s Timing */
[all …]
/linux/drivers/mmc/host/
H A Dsdhci_am654.c1 // SPDX-License-Identifier: GPL-2.0
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pltfm.h"
88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1
107 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
108 "ti,itap-del-sel-legacy",
110 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
111 "ti,itap-del-sel-mmc-hs",
[all …]
/linux/drivers/memory/samsung/
H A Dexynos-srom.c1 // SPDX-License-Identifier: GPL-2.0
6 // Exynos - SROM Controller support
17 #include "exynos-srom.h"
71 u32 timing[6]; in exynos_srom_configure_bank() local
75 return -EINVAL; in exynos_srom_configure_bank()
76 if (of_property_read_u32(np, "reg-io-width", &width)) in exynos_srom_configure_bank()
78 if (of_property_read_bool(np, "samsung,srom-page-mode")) in exynos_srom_configure_bank()
80 if (of_property_read_u32_array(np, "samsung,srom-timing", timing, in exynos_srom_configure_bank()
81 ARRAY_SIZE(timing))) in exynos_srom_configure_bank()
82 return -EINVAL; in exynos_srom_configure_bank()
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf300t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300t-init-hog {
13 gpio-hog;
15 output-low;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
H A Dtegra124-apalis-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include <dt-bindings/clock/tegra124-car.h>
11 emc-timings-1 {
12 nvidia,ram-code = <1>;
14 timing-12750000 {
15 clock-frequency = <12750000>;
16 nvidia,parent-clock-frequency = <408000000>;
18 clock-names = "emc-parent";
21 timing-20400000 {
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
7 emc-timings-3 {
8 nvidia,ram-code = <3>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
18 clock-frequency = <20400000>;
[all …]
H A Dtegra30-asus-tf300tg.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300tg-init-hog {
13 gpio-hog;
28 output-low;
39 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
47 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
55 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
/linux/arch/sparc/include/asm/
H A Dchmctrl.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #define CHMCTRL_TCTRL1 0x00 /* Memory Timing Control I */
7 #define CHMCTRL_TCTRL2 0x08 /* Memory Timing Control II */
8 #define CHMCTRL_TCTRL3 0x38 /* Memory Timing Control III */
9 #define CHMCTRL_TCTRL4 0x40 /* Memory Timing Control IV */
16 /* Memory Timing Control I */
48 /* Memory Timing Control II */
74 /* Memory Timing Control III */
106 /* Memory Timing Control IV */

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