| /linux/drivers/gpu/drm/tegra/ |
| H A D | mipi-phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "mipi-phy.h"
12 * Default D-PHY timings based on MIPI D-PHY specification. Derived from the
13 * valid ranges specified in Section 6.9, Table 14, Page 40 of the D-PHY
16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
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| /linux/drivers/gpu/drm/msm/dsi/phy/ |
| H A D | dsi_phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
8 #include <dt-bindings/phy/phy.h>
13 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
20 v = (tmax - tmin) * percent; in linear_inter()
23 return max_t(s32, min_result, v - 1); in linear_inter()
28 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, in dsi_dphy_timing_calc_clk_zero() argument
35 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
36 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
46 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
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| H A D | dsi_phy_20nm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
13 void __iomem *base = phy->base; in dsi_20nm_dphy_set_timing()
15 writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_20nm_dphy_set_timing()
17 writel(DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail), in dsi_20nm_dphy_set_timing()
19 writel(DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare), in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
24 writel(DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit), in dsi_20nm_dphy_set_timing()
26 writel(DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero), in dsi_20nm_dphy_set_timing()
28 writel(DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare), in dsi_20nm_dphy_set_timing()
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| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
48 * When we change the timing to a timing with a parent that has the same
50 * timing that has a different clock source.
105 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
120 struct emc_timing *timing = NULL; in emc_determine_rate() local
125 for (k = 0; k < tegra->num_timings; k++) { in emc_determine_rate()
126 if (tegra->timings[k].ram_code == ram_code) in emc_determine_rate()
130 for (t = k; t < tegra->num_timings; t++) { in emc_determine_rate()
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_validation.c | 27 * This file owns timing validation against various link limitations. (ex.
38 static uint32_t get_tmds_output_pixel_clock_100hz(const struct dc_crtc_timing *timing) in get_tmds_output_pixel_clock_100hz() argument
41 uint32_t pxl_clk = timing->pix_clk_100hz; in get_tmds_output_pixel_clock_100hz()
43 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) in get_tmds_output_pixel_clock_100hz()
45 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) in get_tmds_output_pixel_clock_100hz()
48 if (timing->display_color_depth == COLOR_DEPTH_101010) in get_tmds_output_pixel_clock_100hz()
50 else if (timing->display_color_depth == COLOR_DEPTH_121212) in get_tmds_output_pixel_clock_100hz()
57 const struct dc_crtc_timing *timing, in dp_active_dongle_validate_timing() argument
60 const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps; in dp_active_dongle_validate_timing()
62 switch (dpcd_caps->dongle_type) { in dp_active_dongle_validate_timing()
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| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_encoder_phys_vid.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
18 (e) && (e)->parent ? \
19 (e)->parent->base.id : -1, \
20 (e) && (e)->hw_intf ? \
21 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
24 (e) && (e)->parent ? \
25 (e)->parent->base.id : -1, \
26 (e) && (e)->hw_intf ? \
27 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| H A D | timing.c | 26 #include <subdev/bios/timing.h>
33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
51 return timing; in nvbios_timingTe()
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| /linux/drivers/video/fbdev/ |
| H A D | gbefb.c | 4 * Copyright (C) 1999 Silicon Graphics, Inc. - Jeffrey Newquist
5 * Copyright (C) 2002 Vivien Chappelier <vivien.chappelier@linux-mips.org>
14 #include <linux/dma-mapping.h>
37 struct gbe_timing_info timing; member
44 /* macro for fastest write-though access to the framebuffer */
63 #define TILE_MASK (TILE_SIZE - 1)
87 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
102 .height = -1,
103 .width = -1,
133 .height = -1,
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/ |
| H A D | dcn201_optc.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
32 optc1->tg_regs->reg
35 optc1->base.ctx
39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
46 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); in optc201_triplebuffer_lock()
70 const struct dc_crtc_timing *timing) in optc201_validate_timing() argument
77 ASSERT(timing != NULL); in optc201_validate_timing()
79 v_blank = (timing->v_total - timing->v_addressable - in optc201_validate_timing()
80 timing->v_border_top - timing->v_border_bottom); in optc201_validate_timing()
82 h_blank = (timing->h_total - timing->h_addressable - in optc201_validate_timing()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| H A D | dml21_translation_helper.c | 1 // SPDX-License-Identifier: MIT
21 switch (in_dc->ctx->dce_version) { in dml21_init_socbb_params()
24 if (config->bb_from_dmub) in dml21_init_socbb_params()
25 soc_bb = config->bb_from_dmub; in dml21_init_socbb_params()
33 memcpy(&dml_init->soc_bb, soc_bb, sizeof(struct dml2_soc_bb)); in dml21_init_socbb_params()
36 memcpy(&dml_init->soc_bb.qos_parameters, qos_params, sizeof(struct dml2_soc_qos_parameters)); in dml21_init_socbb_params()
42 memcpy(&dml_init->soc_bb, &config->external_socbb_ip_params->soc_bb, sizeof(struct dml2_soc_bb)); in dml21_external_socbb_params()
48 …memcpy(&dml_init->ip_caps, &config->external_socbb_ip_params->ip_params, sizeof(struct dml2_ip_cap… in dml21_external_ip_params()
57 switch (in_dc->ctx->dce_version) { in dml21_init_ip_params()
63 memcpy(&dml_init->ip_caps, ip_caps, sizeof(struct dml2_ip_capabilities)); in dml21_init_ip_params()
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| /linux/drivers/memory/tegra/ |
| H A D | tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
15 #include <linux/interconnect-provider.h>
512 /* protect shared rate-change code path */
516 /* Timing change sequence functions */
521 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
522 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
530 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
533 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
539 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
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| H A D | tegra30-emc.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
18 #include <linux/interconnect-provider.h>
392 /* protect shared rate-change code path */
403 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
405 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
409 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
422 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
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| /linux/drivers/video/fbdev/via/ |
| H A D | via_modesetting.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
12 #include <linux/via-core.h>
18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/ |
| H A D | dc_dsc.c | 34 dsc->ctx->logger
55 /* Need to account for padding due to pixel-to-symbol packing
59 const struct dc_crtc_timing *timing, const uint32_t kbps) in apply_128b_132b_stream_overhead() argument
66 if (!timing->flags.DSC) { in apply_128b_132b_stream_overhead()
71 bpp = dc_fixpt_div_int(bpp, timing->pix_clk_100hz / 10); in apply_128b_132b_stream_overhead()
73 /* Symbols_per_HActive = HActive * bpp / (4 lanes * 32-bit symbol size) in apply_128b_132b_stream_overhead()
76 overhead_factor = dc_fixpt_from_int(timing->h_addressable); in apply_128b_132b_stream_overhead()
91 const struct dc_crtc_timing *timing, in dc_bandwidth_in_kbps_from_timing() argument
97 if (timing->flags.DSC) in dc_bandwidth_in_kbps_from_timing()
98 return dc_dsc_stream_bandwidth_in_kbps(timing, in dc_bandwidth_in_kbps_from_timing()
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| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| H A D | dce110_timing_generator_v.c | 42 tg->ctx->logger
45 * DCE11 Timing Generator Implementation
64 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
69 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
74 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
84 value = dm_read_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
90 dm_write_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
94 * tg->funcs->disable_stereo(tg); in dce110_timing_generator_v_disable_crtc()
102 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_blank_crtc()
116 dm_write_reg(tg->ctx, addr, value); in dce110_timing_generator_v_blank_crtc()
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| /linux/drivers/gpu/drm/sti/ |
| H A D | sti_awg_utils.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #define AWG_DELAY (-5)
48 if (fwparams->instruction_offset >= AWG_MAX_INST) { in awg_generate_instr()
50 return -EINVAL; in awg_generate_instr()
57 arg--; /* pixel adjustment */ in awg_generate_instr()
58 arg_tmp--; in awg_generate_instr()
105 return -EINVAL; in awg_generate_instr()
108 arg_tmp = arg_tmp - arg; in awg_generate_instr()
113 fwparams->ram_code[fwparams->instruction_offset] = in awg_generate_instr()
115 fwparams->instruction_offset++; in awg_generate_instr()
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| /linux/drivers/media/rc/img-ir/ |
| H A D | img-ir-hw.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright 2010-2014 Imagination Technologies Ltd.
12 #include <media/rc-core.h>
18 #define IMG_IR_CODETYPE_BIPHASE 0x2 /* RC-5/6 */
19 #define IMG_IR_CODETYPE_2BITPULSEPOS 0x3 /* RC-MM */
22 /* Timing information */
25 * struct img_ir_control - Decoder control settings
53 * struct img_ir_timing_range - range of timing values
54 * @min: Minimum timing value
55 * @max: Maximum timing value (if < @min, this will be set to @min during
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| H A D | ramnv50.c | 34 #include <subdev/bios/timing.h>
71 #define T(t) cfg->timing_10_##t
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
75 struct nvbios_ramcfg *cfg = &ram->base.target.bios; in nv50_ram_timing_calc()
76 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in nv50_ram_timing_calc()
77 struct nvkm_device *device = subdev->device; in nv50_ram_timing_calc()
86 switch ((!T(CWL)) * ram->base.type) { in nv50_ram_timing_calc()
88 T(CWL) = T(CL) - 1; in nv50_ram_timing_calc()
96 if (device->chipset == 0xa0) { in nv50_ram_timing_calc()
97 unkt3b = 0x19 + ram->base.next->bios.rammap_00_16_40; in nv50_ram_timing_calc()
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| /linux/drivers/leds/ |
| H A D | leds-expresswire.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/leds-expresswire.h>
18 gpiod_set_value_cansleep(props->ctrl_gpio, 0); in expresswire_power_off()
19 usleep_range(props->timing.poweroff_us, props->timing.poweroff_us * 2); in expresswire_power_off()
25 gpiod_set_value(props->ctrl_gpio, 1); in expresswire_enable()
26 udelay(props->timing.detect_delay_us); in expresswire_enable()
27 gpiod_set_value(props->ctrl_gpio, 0); in expresswire_enable()
28 udelay(props->timing.detect_us); in expresswire_enable()
29 gpiod_set_value(props->ctrl_gpio, 1); in expresswire_enable()
35 gpiod_set_value(props->ctrl_gpio, 1); in expresswire_start()
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| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | sdhci-am654.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 44 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn32_helper_calculate_mall_bytes_for_cursor()
45 uint32_t cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; in dcn32_helper_calculate_mall_bytes_for_cursor()
48 switch (pipe_ctx->stream->cursor_attributes.color_format) { in dcn32_helper_calculate_mall_bytes_for_cursor()
67 if (pipe_ctx->stream->cursor_position.enable && (ignore_cursor_buf || in dcn32_helper_calculate_mall_bytes_for_cursor()
72 cursor_mall_size_bytes = ((cursor_size + DCN3_2_MALL_MBLK_SIZE_BYTES - 1) / in dcn32_helper_calculate_mall_bytes_for_cursor()
94 if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) { in dcn32_helper_calculate_num_ways_for_subvp()
95 if (dc->debug.force_subvp_num_ways) { in dcn32_helper_calculate_num_ways_for_subvp()
96 return dc->debug.force_subvp_num_ways; in dcn32_helper_calculate_num_ways_for_subvp()
97 } else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { in dcn32_helper_calculate_num_ways_for_subvp()
98 …return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_s… in dcn32_helper_calculate_num_ways_for_subvp()
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| /linux/drivers/ata/ |
| H A D | pata_triflex.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_triflex.c - Compaq PATA for new ATA layer
15 * Copyright (C) 2002 Hewlett-Packard Development Group, L.P.
36 * triflex_prereset - probe begin
50 struct ata_port *ap = link->ap; in triflex_prereset()
51 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in triflex_prereset()
53 if (!pci_test_config_bits(pdev, &triflex_enable_bits[ap->port_no])) in triflex_prereset()
54 return -ENOENT; in triflex_prereset()
62 * triflex_load_timing - timing configuration
75 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in triflex_load_timing()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_mall_phantom.c | 1 /* SPDX-License-Identifier: MIT */
49 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { in dml2_helper_calculate_num_ways_for_subvp()
50 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dml2_helper_calculate_num_ways_for_subvp()
53 if (pipe->stream && pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe && in dml2_helper_calculate_num_ways_for_subvp()
54 ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) { in dml2_helper_calculate_num_ways_for_subvp()
55 bytes_per_pixel = pipe->plane_state->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4; in dml2_helper_calculate_num_ways_for_subvp()
56 mblk_width = ctx->config.mall_cfg.mblk_width_pixels; in dml2_helper_calculate_num_ways_for_subvp()
57 …blk_height = bytes_per_pixel == 4 ? mblk_width = ctx->config.mall_cfg.mblk_height_4bpe_pixels : ct… in dml2_helper_calculate_num_ways_for_subvp()
59 /* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) - in dml2_helper_calculate_num_ways_for_subvp()
62 full_vp_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x + in dml2_helper_calculate_num_ways_for_subvp()
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| /linux/Documentation/driver-api/memory-devices/ |
| H A D | ti-gpmc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 * Pseudo-SRAM devices
20 GPMC generic timing calculation:
29 generic timing routine was developed to achieve above requirements.
37 happen that timing as specified by peripheral datasheet is not present
38 in timing structure, in this scenario, try to correlate peripheral
39 timing to the one available. If that doesn't work, try to add a new
40 field as required by peripheral, educate generic timing routine to
45 Generic timing routine has been verified to work properly on
48 A word of caution: generic timing routine has been developed based
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| /linux/drivers/gpu/drm/amd/display/dc/dce120/ |
| H A D | dce120_timing_generator.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
43 generic_reg_update_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
46 generic_reg_set_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
91 tg->ctx, in dce120_timing_generator_is_in_vertical_blank()
93 tg110->offsets.crtc); in dce120_timing_generator_is_in_vertical_blank()
100 /* determine if given timing can be supported by TG */
103 const struct dc_crtc_timing *timing, in dce120_timing_generator_validate_timing() argument
106 uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; in dce120_timing_generator_validate_timing()
108 (timing->v_total - timing->v_addressable - in dce120_timing_generator_validate_timing()
109 timing->v_border_top - timing->v_border_bottom) * in dce120_timing_generator_validate_timing()
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