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/linux/Documentation/devicetree/bindings/timer/
H A Dti,timer-dm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI dual-mode timer
10 - Tony Lindgren <tony@atomide.com>
13 The TI dual-mode timer is a general purpose timer with PWM capabilities.
18 - items:
19 - enum:
20 - ti,am335x-timer
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/linux/arch/arm64/boot/dts/amlogic/
H A Damlogic-a4-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h>
10 timer {
11 compatible = "arm,armv8-timer";
19 compatible = "arm,psci-1.0";
23 xtal: xtal-clk {
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
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H A Damlogic-s7d.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/amlogic,pinctrl.h>
10 #include <dt-bindings/power/amlogic,s7d-pwrc.h>
14 #address-cells = <2>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a55";
21 enable-method = "psci";
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H A Damlogic-s7.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/amlogic,pinctrl.h>
10 #include <dt-bindings/power/amlogic,s7-pwrc.h>
14 #address-cells = <2>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a55";
21 enable-method = "psci";
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/linux/arch/arm64/boot/dts/sprd/
H A Dums9620.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
50 compatible = "arm,cortex-a55";
52 enable-method = "psci";
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/linux/Documentation/devicetree/bindings/rtc/
H A Damlogic,meson-vrtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/amlogic,meson-vrtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
17 application processors (AP) and the secure co-processor (SCP.) When
19 program an always-on timer before going sleep. When the timer expires,
23 - $ref: rtc.yaml#
28 - amlogic,meson-vrtc
34 - compatible
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/linux/arch/arm64/boot/dts/blaize/
H A Dblaize-blzp1600.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-a53";
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/linux/drivers/watchdog/
H A Dkeembay_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Watchdog driver for Intel Keem Bay non-secure watchdog.
8 #include <linux/arm-smccc.h>
19 /* Non-secure watchdog register offsets */
60 return readl(wdt->base + offset); in keembay_wdt_readl()
65 writel(WDT_UNLOCK, wdt->base + TIM_SAFE); in keembay_wdt_writel()
66 writel(val, wdt->base + offset); in keembay_wdt_writel()
73 keembay_wdt_writel(wdt, TIM_WATCHDOG, wdog->timeout * wdt->rate); in keembay_wdt_set_timeout_reg()
81 if (wdog->pretimeout) in keembay_wdt_set_pretimeout_reg()
82 th_val = wdog->timeout - wdog->pretimeout; in keembay_wdt_set_pretimeout_reg()
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H A Domap_wdt.c1 // SPDX-License-Identifier: GPL-2.0
5 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
15 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
20 * 1. Modified to support OMAP1610 32-KHz watchdog timer
41 #include <linux/platform_data/omap-wd-timer.h>
72 void __iomem *base = wdev->base; in omap_wdt_reload()
78 wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern; in omap_wdt_reload()
79 writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR)); in omap_wdt_reload()
89 void __iomem *base = wdev->base; in omap_wdt_enable()
103 void __iomem *base = wdev->base; in omap_wdt_disable()
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/linux/include/dt-bindings/gce/
H A Dmt8186-gce.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
79 /* VCU: poll with timeout for GPR timer */
351 * Note that token 512 to 639 may set secure
367 /* Notify normal CMDQ there are some secure task done
368 * MUST NOT CHANGE, this token sync with secure world
386 * There are 15 32-bit GPR, 3 GPR form a set
387 * (64-bit for address, 32-bit for value)
400 /* event for gpr timer, used in sleep and poll with timeout */
/linux/arch/arm/mach-omap2/
H A Dtimer.c2 * linux/arch/arm/mach-omap2/timer.c
4 * OMAP2 GP timer support.
16 * OMAP Dual-mode timer framework support by Timo Teras
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
35 #include "omap-secure.h"
50 * The realtime counter also called master counter, is a free-running
52 * by the CPU local timer peripherals in the MPU cluster. The timer counts
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
7 obj-y := id.o io.o control.o devices.o fb.o pm.o \
8 common.o dma.o omap-headsmp.o sram.o
10 hwmod-common = omap_hwmod.o \
15 clock-common = clock.o
16 secure-common = omap-smc.o omap-secure.o
18 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
19 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
20 obj-$(CONFIG_ARCH_OMAP4) += $(secure-common)
21 obj-$(CONFIG_SOC_AM33XX) += $(secure-common)
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/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
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/linux/drivers/gpu/drm/nouveau/nvkm/falcon/
H A Dv1.c26 #include <subdev/timer.h>
30 u32 size, u16 tag, u8 port, bool secure) in nvkm_falcon_v1_load_imem() argument
36 size -= rem; in nvkm_falcon_v1_load_imem()
38 reg = start | BIT(24) | (secure ? BIT(28) : 0); in nvkm_falcon_v1_load_imem()
58 extra & (BIT(rem * 8) - 1)); in nvkm_falcon_v1_load_imem()
74 size -= rem; in nvkm_falcon_v1_load_dmem()
88 extra & (BIT(rem * 8) - 1)); in nvkm_falcon_v1_load_dmem()
H A Dbase.c25 #include <subdev/timer.h>
31 if (falcon->func->intr_retrigger) in nvkm_falcon_intr_retrigger()
32 falcon->func->intr_retrigger(falcon); in nvkm_falcon_intr_retrigger()
38 if (!falcon->func->riscv_active) in nvkm_falcon_riscv_active()
41 return falcon->func->riscv_active(falcon); in nvkm_falcon_riscv_active()
48 case IMEM: return falcon->func->imem_dma; in nvkm_falcon_dma()
49 case DMEM: return falcon->func->dmem_dma; in nvkm_falcon_dma()
66 if (WARN_ON(!dma->xfer)) in nvkm_falcon_dma_wr()
67 return -EINVAL; in nvkm_falcon_dma_wr()
74 FLCN_DBG(falcon, "%s %08x <- %08x bytes at %08x (%010llx %08x)", in nvkm_falcon_dma_wr()
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/linux/Documentation/devicetree/bindings/watchdog/
H A Dintel,keembay-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/intel,keembay-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Keem Bay SoC non-secure Watchdog Timer
10 - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
13 - $ref: watchdog.yaml#
18 - intel,keembay-wdt
28 - description: interrupt specifier for threshold interrupt line
29 - description: interrupt specifier for timeout interrupt line
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/linux/arch/arm/mach-nomadik/
H A Dcpu-8815.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <asm/mach-types.h>
15 * These are the only hard-coded address offsets we still have to use.
24 #define NOMADIK_USB_BASE 0x10170000 /* USB-OTG conf reg base */
26 #define NOMADIK_SHA1_BASE 0x10190000 /* SHA-1 Processor */
31 #define NOMADIK_MTU0_BASE 0x101E2000 /* Multiple Timer 0 */
32 #define NOMADIK_MTU1_BASE 0x101E3000 /* Multiple Timer 1 */
40 #define NOMADIK_SCR_BASE 0x101EF000 /* Secure Control registers */
44 #define NOMADIK_SSIRx_BASE 0x101F3000 /* SSI 8-ch rx interface */
45 #define NOMADIK_SSITx_BASE 0x101F4000 /* SSI 8-ch tx interface */
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dgm20b.c27 #include <subdev/timer.h>
39 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm20b_gr_acr_bld_patch()
46 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm20b_gr_acr_bld_patch()
48 flcn_bl_dmem_desc_dump(&acr->subdev, &hdr); in gm20b_gr_acr_bld_patch()
55 const u64 base = lsfw->offset.img + lsfw->app_start_offset; in gm20b_gr_acr_bld_write()
56 const u64 code = (base + lsfw->app_resident_code_offset) >> 8; in gm20b_gr_acr_bld_write()
57 const u64 data = (base + lsfw->app_resident_data_offset) >> 8; in gm20b_gr_acr_bld_write()
61 .non_sec_code_off = lsfw->app_resident_code_offset, in gm20b_gr_acr_bld_write()
62 .non_sec_code_size = lsfw->app_resident_code_size, in gm20b_gr_acr_bld_write()
63 .code_entry_point = lsfw->app_imem_entry, in gm20b_gr_acr_bld_write()
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8qxp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2020 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/clock/imx8-lpcg.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
15 #include <dt-bindings/thermal/thermal.h>
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/linux/arch/arm/boot/dts/realtek/
H A Drtd1195.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 * Copyright (c) 2017-2019 Andreas Färber
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/realtek,rtd1195.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a7";
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/linux/include/uapi/linux/
H A Dvirtio_ids.h46 #define VIRTIO_ID_CLOCK 17 /* virtio clock/timer */
58 #define VIRTIO_ID_MAC80211_HWSIM 29 /* virtio mac80211-hwsim */
62 #define VIRTIO_ID_NITRO_SEC_MOD 33 /* virtio nitro secure module*/
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
22 #interrupt-cells = <3>;
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H A Dk3-am62a-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
24 #address-cells = <2>;
25 #size-cells = <2>;
27 #interrupt-cells = <3>;
[all …]
/linux/arch/arm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
50 # https://github.com/llvm/llvm-project/commit/d130f402642fba3d065aacb506cb061c899558de
168 The ARM series is a line of low-power-consumption RISC chip designs
170 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
171 manufactured, but legacy ARM-based PC hardware remains popular in
179 relocations. The combined range is -/+ 256 MiB, which is usually
272 Patch phys-to-virt and virt-to-phys translation functions at
276 This can only be used with non-XIP MMU kernels where the base
322 bool "MMU-based Paged Memory Management Support"
325 Select if you want MMU-based virtualised addressing space
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/linux/tools/arch/x86/include/asm/
H A Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define NCAPINTS 22 /* N 32-bit words worth of info */
9 #define NBUGINTS 2 /* N 32-bit bug flags */
17 * please update the table in kernel/cpu/cpuid-deps.c as well.
20 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
26 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
37 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */
47 #define X86_FEATURE_HT ( 0*32+28) /* "ht" Hyper-Threading */
49 #define X86_FEATURE_IA64 ( 0*32+30) /* "ia64" IA-64 processor */
52 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
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