Home
last modified time | relevance | path

Searched +full:timer +full:- +full:secure (Results 1 – 25 of 124) sorted by relevance

12345

/linux/arch/arm64/boot/dts/arm/
H A Dcorstone1000.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
21 stdout-path = "serial0:115200n8";
25 #address-cells = <1>;
26 #size-cells = <0>;
30 compatible = "arm,cortex-a35";
32 enable-method = "psci";
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dti,timer-dm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI dual-mode timer
10 - Tony Lindgren <tony@atomide.com>
13 The TI dual-mode timer is a general purpose timer with PWM capabilities.
18 - items:
19 - enum:
20 - ti,am335x-timer
[all …]
H A Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM architected timer
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
15 physical and optional virtual timer per frame.
[all …]
/linux/arch/arm/mach-shmobile/
H A Dsetup-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Generation 2 support
22 { .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" },
23 { .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
24 { .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
25 { .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
26 { .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" },
27 { .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" },
42 if (match->data) in get_extal_freq()
43 idx = of_property_match_string(cpg, "clock-names", match->data); in get_extal_freq()
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Damlogic-a4-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h>
10 timer {
11 compatible = "arm,armv8-timer";
19 compatible = "arm,psci-1.0";
23 xtal: xtal-clk {
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
[all …]
/linux/arch/arm/mach-at91/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
18 bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
178 bool "Periodic Interval Timer (PIT) support"
184 Timer. It has a relatively low resolution and the TC Block clocksource
188 bool "Timer Counter Blocks (TCB) support"
194 On platforms with 16-bit counters, two timer channels are combined
195 to make a single 32-bit timer.
199 bool "64-bit Periodic Interval Timer (PIT64B) support"
204 clocksource and clockevent (SAMA7G5) based on Microchip 64-bit
205 Periodic Interval Timer.
[all …]
/linux/arch/arm64/boot/dts/intel/
H A Dkeembay-soc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
[all …]
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/linux/arch/arm64/boot/dts/sprd/
H A Dums9620.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
50 compatible = "arm,cortex-a55";
52 enable-method = "psci";
[all …]
/linux/Documentation/devicetree/bindings/rtc/
H A Damlogic,meson-vrtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/amlogic,meson-vrtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
17 application processors (AP) and the secure co-processor (SCP.) When
19 program an always-on timer before going sleep. When the timer expires,
23 - $ref: rtc.yaml#
28 - amlogic,meson-vrtc
34 - compatible
[all …]
/linux/drivers/acpi/arm64/
H A Dgtdt.c1 // SPDX-License-Identifier: GPL-2.0-only
23 * struct acpi_gtdt_descriptor - Store the key info of GTDT for all functions
26 * @platform_timer: The pointer to the start of Platform Timer Structure
45 gh->length != 0 && in platform_timer_valid()
46 platform_timer + gh->length <= acpi_gtdt_desc.gtdt_end); in platform_timer_valid()
53 return platform_timer + gh->length; in next_platform_timer()
64 return gh->type == ACPI_GTDT_TYPE_TIMER_BLOCK; in is_timer_block()
72 if (gh->type != ACPI_GTDT_TYPE_WATCHDOG) in is_non_secure_watchdog()
75 return !(wd->timer_flags & ACPI_GTDT_WATCHDOG_SECURE); in is_non_secure_watchdog()
92 * acpi_gtdt_map_ppi() - Map the PPIs of per-cpu arch_timer.
[all …]
/linux/arch/arm64/boot/dts/blaize/
H A Dblaize-blzp1600.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-a53";
[all …]
/linux/include/dt-bindings/gce/
H A Dmt8186-gce.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
79 /* VCU: poll with timeout for GPR timer */
351 * Note that token 512 to 639 may set secure
367 /* Notify normal CMDQ there are some secure task done
368 * MUST NOT CHANGE, this token sync with secure world
386 * There are 15 32-bit GPR, 3 GPR form a set
387 * (64-bit for address, 32-bit for value)
400 /* event for gpr timer, used in sleep and poll with timeout */
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/linux/arch/arm/mach-omap2/
H A Dtimer.c2 * linux/arch/arm/mach-omap2/timer.c
4 * OMAP2 GP timer support.
16 * OMAP Dual-mode timer framework support by Timo Teras
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
35 #include "omap-secure.h"
50 * The realtime counter also called master counter, is a free-running
52 * by the CPU local timer peripherals in the MPU cluster. The timer counts
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
7 obj-y := id.o io.o control.o devices.o fb.o pm.o \
8 common.o dma.o omap-headsmp.o sram.o
10 hwmod-common = omap_hwmod.o \
15 clock-common = clock.o
16 secure-common = omap-smc.o omap-secure.o
18 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
19 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
20 obj-$(CONFIG_ARCH_OMAP4) += $(secure-common)
21 obj-$(CONFIG_SOC_AM33XX) += $(secure-common)
[all …]
/linux/drivers/watchdog/
H A Dkeembay_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Watchdog driver for Intel Keem Bay non-secure watchdog.
8 #include <linux/arm-smccc.h>
20 /* Non-secure watchdog register offsets */
61 return readl(wdt->base + offset); in keembay_wdt_readl()
66 writel(WDT_UNLOCK, wdt->base + TIM_SAFE); in keembay_wdt_writel()
67 writel(val, wdt->base + offset); in keembay_wdt_writel()
74 keembay_wdt_writel(wdt, TIM_WATCHDOG, wdog->timeout * wdt->rate); in keembay_wdt_set_timeout_reg()
82 if (wdog->pretimeout) in keembay_wdt_set_pretimeout_reg()
83 th_val = wdog->timeout - wdog->pretimeout; in keembay_wdt_set_pretimeout_reg()
[all …]
H A Domap_wdt.c1 // SPDX-License-Identifier: GPL-2.0
5 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
15 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
20 * 1. Modified to support OMAP1610 32-KHz watchdog timer
42 #include <linux/platform_data/omap-wd-timer.h>
73 void __iomem *base = wdev->base; in omap_wdt_reload()
79 wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern; in omap_wdt_reload()
80 writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR)); in omap_wdt_reload()
90 void __iomem *base = wdev->base; in omap_wdt_enable()
104 void __iomem *base = wdev->base; in omap_wdt_disable()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/falcon/
H A Dv1.c26 #include <subdev/timer.h>
30 u32 size, u16 tag, u8 port, bool secure) in nvkm_falcon_v1_load_imem() argument
36 size -= rem; in nvkm_falcon_v1_load_imem()
38 reg = start | BIT(24) | (secure ? BIT(28) : 0); in nvkm_falcon_v1_load_imem()
58 extra & (BIT(rem * 8) - 1)); in nvkm_falcon_v1_load_imem()
74 size -= rem; in nvkm_falcon_v1_load_dmem()
88 extra & (BIT(rem * 8) - 1)); in nvkm_falcon_v1_load_dmem()
H A Dbase.c25 #include <subdev/timer.h>
31 if (falcon->func->intr_retrigger) in nvkm_falcon_intr_retrigger()
32 falcon->func->intr_retrigger(falcon); in nvkm_falcon_intr_retrigger()
38 if (!falcon->func->riscv_active) in nvkm_falcon_riscv_active()
41 return falcon->func->riscv_active(falcon); in nvkm_falcon_riscv_active()
48 case IMEM: return falcon->func->imem_dma; in nvkm_falcon_dma()
49 case DMEM: return falcon->func->dmem_dma; in nvkm_falcon_dma()
66 if (WARN_ON(!dma->xfer)) in nvkm_falcon_dma_wr()
67 return -EINVAL; in nvkm_falcon_dma_wr()
74 FLCN_DBG(falcon, "%s %08x <- %08x bytes at %08x (%010llx %08x)", in nvkm_falcon_dma_wr()
[all …]
/linux/Documentation/devicetree/bindings/watchdog/
H A Dintel,keembay-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/intel,keembay-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Keem Bay SoC non-secure Watchdog Timer
10 - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
13 - $ref: watchdog.yaml#
18 - intel,keembay-wdt
28 - description: interrupt specifier for threshold interrupt line
29 - description: interrupt specifier for timeout interrupt line
[all …]
/linux/arch/arm/mach-nomadik/
H A Dcpu-8815.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <asm/mach-types.h>
15 * These are the only hard-coded address offsets we still have to use.
24 #define NOMADIK_USB_BASE 0x10170000 /* USB-OTG conf reg base */
26 #define NOMADIK_SHA1_BASE 0x10190000 /* SHA-1 Processor */
31 #define NOMADIK_MTU0_BASE 0x101E2000 /* Multiple Timer 0 */
32 #define NOMADIK_MTU1_BASE 0x101E3000 /* Multiple Timer 1 */
40 #define NOMADIK_SCR_BASE 0x101EF000 /* Secure Control registers */
44 #define NOMADIK_SSIRx_BASE 0x101F3000 /* SSI 8-ch rx interface */
45 #define NOMADIK_SSITx_BASE 0x101F4000 /* SSI 8-ch tx interface */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dgm20b.c27 #include <subdev/timer.h>
39 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm20b_gr_acr_bld_patch()
46 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm20b_gr_acr_bld_patch()
48 flcn_bl_dmem_desc_dump(&acr->subdev, &hdr); in gm20b_gr_acr_bld_patch()
55 const u64 base = lsfw->offset.img + lsfw->app_start_offset; in gm20b_gr_acr_bld_write()
56 const u64 code = (base + lsfw->app_resident_code_offset) >> 8; in gm20b_gr_acr_bld_write()
57 const u64 data = (base + lsfw->app_resident_data_offset) >> 8; in gm20b_gr_acr_bld_write()
61 .non_sec_code_off = lsfw->app_resident_code_offset, in gm20b_gr_acr_bld_write()
62 .non_sec_code_size = lsfw->app_resident_code_size, in gm20b_gr_acr_bld_write()
63 .code_entry_point = lsfw->app_imem_entry, in gm20b_gr_acr_bld_write()
[all …]
/linux/arch/arm64/boot/dts/nuvoton/
H A Dma35d1.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Shan-Chun Hung <schung@nuvoton.com>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
12 #include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
[all …]

12345