Home
last modified time | relevance | path

Searched +full:timer +full:- +full:adjust (Results 1 – 25 of 193) sorted by relevance

12345678

/linux/drivers/clocksource/
H A Darm_global_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
59 * To get the value from the Global Timer Counter register proceed as follows:
60 * 1. Read the upper 32-bit timer counter register
61 * 2. Read the lower 32-bit timer counter register
62 * 3. Read the upper 32-bit timer counter register again. If the value is
63 * different to the 32-bit upper value read previously, go back to step 2.
64 * Otherwise the 64-bit timer counter value is correct.
93 * 1. Clear the Comp Enable bit in the Timer Control Register.
94 * 2. Write the lower 32-bit Comparator Value Register.
95 * 3. Write the upper 32-bit Comparator Value Register.
[all …]
H A Dtimer-cadence-ttc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * This file contains driver for the Cadence Triple Timer Counter Rev 06
5 * Copyright (C) 2011-2013 Xilinx
7 * based on arch/mips/kernel/time.c timer driver
23 * This driver configures the 2 16/32-bit count-up timers as follows:
25 * T1: Timer 1, clocksource for generic timekeeping
26 * T2: Timer 2, clockevent source for hrtimers
27 * T3: Timer 3, <unused>
29 * The input frequency to the timer module for emulation is 2.5MHz which is
30 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
[all …]
H A Dscx200_hrt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * high-resolution timer. The Geode SC-1100 (at least) has a buggy
8 * given as a boot-arg. In its absence, the Generic Timekeeping code
9 * will detect and de-rate the bad TSC, allowing this timer to take
12 * Based on work by John Stultz, and Ted Phelps (in a 2.6.12-rc6 patch)
29 MODULE_PARM_DESC(ppm, "+-adjust to actual XO freq (ppm)");
31 /* HiRes Timer configuration register address */
35 #define HR_TMEN (1 << 0) /* timer interrupt enable */
37 #define HR_TM27MPD (1 << 2) /* 1 turns off input clock (power-down) */
39 /* The base timer frequency, * 27 if selected */
[all …]
H A Dtimer-pxa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-pxa/time.c
8 * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
26 #define OSMR0 0x00 /* OS Timer 0 Match Register */
27 #define OSMR1 0x04 /* OS Timer 1 Match Register */
28 #define OSMR2 0x08 /* OS Timer 2 Match Register */
29 #define OSMR3 0x0C /* OS Timer 3 Match Register */
31 #define OSCR 0x10 /* OS Timer Counter Register */
32 #define OSSR 0x14 /* OS Timer Status Register */
33 #define OWER 0x18 /* OS Timer Watchdog Enable Register */
[all …]
H A Dtimer-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Inspired by time-efm32.c from Uwe Kleine-Koenig
23 #include "timer-of.h"
54 * stm32_timer_of_bits_set - set accessor helper
58 * Accessor helper to set the number of bits in the timer-of private
64 struct stm32_timer_private *pd = to->private_data; in stm32_timer_of_bits_set()
66 pd->bits = bits; in stm32_timer_of_bits_set()
70 * stm32_timer_of_bits_get - get accessor helper
73 * Accessor helper to get the number of bits in the timer-of private
80 struct stm32_timer_private *pd = to->private_data; in stm32_timer_of_bits_get()
[all …]
/linux/drivers/net/ethernet/freescale/
H A Dfec_ptp.c1 // SPDX-License-Identifier: GPL-2.0
92 * fec_ptp_read - read raw cycle counter (to be used by time counter)
105 tempval = readl(fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
107 writel(tempval, fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
109 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE) in fec_ptp_read()
112 return readl(fep->hwp + FEC_ATIME); in fec_ptp_read()
120 * This function enables the PPS output on the timer channel.
129 spin_lock_irqsave(&fep->tmreg_lock, flags); in fec_ptp_enable_pps()
131 if (fep->perout_enable) { in fec_ptp_enable_pps()
132 spin_unlock_irqrestore(&fep->tmreg_lock, flags); in fec_ptp_enable_pps()
[all …]
/linux/drivers/net/ethernet/intel/idpf/
H A Didpf_ptp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 * struct idpf_ptp_cmd - PTP command masks
19 /* struct idpf_ptp_dev_clk_regs - PTP device registers
28 * @shadj_l: low part of the shadow adjust register
29 * @shadj_h: high part of the shadow adjust register
32 * @phy_shadj_l: low part of the PHY shadow adjust register
33 * @phy_shadj_h: high part of the PHY shadow adjust register
43 /* PHY timer */
51 /* Main timer adjustments */
57 /* PHY timer adjustments */
[all …]
/linux/drivers/net/ethernet/mellanox/mlx4/
H A Den_clock.c14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
39 /* mlx4_en_read_clock - read raw cycle counter (to be used by time counter)
45 struct mlx4_dev *dev = mdev->dev; in mlx4_en_read_clock()
47 return mlx4_read_clock(dev) & tc->mask; in mlx4_en_read_clock()
55 lo = (u64)be16_to_cpu(ts_cqe->timestamp_lo); in mlx4_en_get_cqe_ts()
56 hi = ((u64)be32_to_cpu(ts_cqe->timestamp_hi) + !lo) << 16; in mlx4_en_get_cqe_ts()
67 seq = read_seqbegin(&mdev->clock_lock); in mlx4_en_get_hwtstamp()
68 nsec = timecounter_cyc2time(&mdev->clock, timestamp); in mlx4_en_get_hwtstamp()
69 } while (read_seqretry(&mdev->clock_lock, seq)); in mlx4_en_get_hwtstamp()
[all …]
/linux/drivers/platform/x86/
H A Dintel_ips.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2009-2010 Intel Corporation
10 * Some Intel Ibex Peak based platforms support so-called "intelligent
25 * close or over our TDP) we don't adjust the clamps more than once every
34 * - dual MCP configs
37 * - handle CPU hotplug
38 * - provide turbo enable/disable api
41 * - CDI 403777, 403778 - Auburndale EDS vol 1 & 2
42 * - CDI 401376 - Ibex Peak EDS
43 * - ref 26037, 26641 - IPS BIOS spec
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dlo.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* G-PHY Local Oscillator */
11 /* Local Oscillator control value-pair. */
67 * the item really expired when the 15 second timer hits, we
69 #define B43_LO_CALIB_EXPIRE (HZ * (30 - 2))
70 #define B43_LO_PWRVEC_EXPIRE (HZ * (30 - 2))
71 #define B43_LO_TXCTL_EXPIRE (HZ * (180 - 4))
74 /* Adjust the Local Oscillator to the saved attenuation
78 /* Adjust to specific values. */
/linux/arch/mips/kernel/
H A Dtime.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include <asm/cpu-features.h>
25 #include <asm/cpu-type.h>
40 struct cpumask *cpus = freq->policy->cpus; in cpufreq_callback()
45 * Skip lpj numbers adjustment if the CPU-freq transition is safe for in cpufreq_callback()
48 if (freq->flags & CPUFREQ_CONST_LOOPS) in cpufreq_callback()
54 glb_lpj_ref_freq = freq->old; in cpufreq_callback()
59 per_cpu(pcp_lpj_ref_freq, cpu) = freq->old; in cpufreq_callback()
64 * Adjust global lpj variable and per-CPU udelay_val number in in cpufreq_callback()
67 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || in cpufreq_callback()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dgm20b.c27 #include <subdev/timer.h>
34 gm20b_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gm20b_gr_acr_bld_patch() argument
39 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm20b_gr_acr_bld_patch()
41 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
42 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
44 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
45 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
46 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm20b_gr_acr_bld_patch()
48 flcn_bl_dmem_desc_dump(&acr->subdev, &hdr); in gm20b_gr_acr_bld_patch()
55 const u64 base = lsfw->offset.img + lsfw->app_start_offset; in gm20b_gr_acr_bld_write()
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_ptp.c4 * Copyright (c) 2003-2017 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
54 * cxgb4_ptp_is_ptp_tx - determine whether TX packet is PTP or not
63 return skb->len >= PTP_MIN_LENGTH && in cxgb4_ptp_is_ptp_tx()
64 skb->len <= PTP_IN_TRANSMIT_PACKET_MAXNUM && in cxgb4_ptp_is_ptp_tx()
65 likely(skb->protocol == htons(ETH_P_IP)) && in cxgb4_ptp_is_ptp_tx()
66 ip_hdr(skb)->protocol == IPPROTO_UDP && in cxgb4_ptp_is_ptp_tx()
67 uh->dest == htons(PTP_EVENT_PORT); in cxgb4_ptp_is_ptp_tx()
75 return (pi->ptp_enable && cxgb4_xmit_with_hwtstamp(skb) && in is_ptp_enabled()
[all …]
/linux/drivers/net/ethernet/intel/e1000e/
H A Dptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
18 * e1000e_phc_adjfine - adjust the frequency of the hardware clock
22 * Adjust the frequency of the PHC cycle counter by the indicated delta from
31 struct e1000_hw *hw = &adapter->hw; in e1000e_phc_adjfine()
42 spin_lock_irqsave(&adapter->systim_lock, flags); in e1000e_phc_adjfine()
52 adapter->ptp_delta = delta; in e1000e_phc_adjfine()
54 spin_unlock_irqrestore(&adapter->systim_lock, flags); in e1000e_phc_adjfine()
60 * e1000e_phc_adjtime - Shift the time of the hardware clock
64 * Adjust the timer by resetting the timecounter structure.
[all …]
/linux/arch/alpha/kernel/
H A Drtc.c1 // SPDX-License-Identifier: GPL-2.0
25 * We don't want to use the rtc-cmos driver, because we don't want to support
26 * alarms, as that would be indistinguishable from timer interrupts.
31 * than 1900, and so it's easy to adjust.
54 /* The epoch was specified on the command-line. */ in init_rtc_epoch()
64 /* PC-like is standard; used for year >= 70 */ in init_rtc_epoch()
90 /* Adjust for non-default epochs. It's easier to depend on the in alpha_rtc_read_time()
91 generic __get_rtc_time and adjust the epoch here than create in alpha_rtc_read_time()
94 int year = tm->tm_year; in alpha_rtc_read_time()
97 year -= 100; in alpha_rtc_read_time()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec2/
H A Dgp102.c26 #include <subdev/timer.h>
35 nvkm_warn(&sec2->engine.subdev, "firmware unavailable\n"); in gp102_sec2_nofw()
45 const char *name = nvkm_acr_lsf_id(msg->falcon_id); in gp102_sec2_acr_bootstrap_falcon_callback()
47 if (msg->error_code) { in gp102_sec2_acr_bootstrap_falcon_callback()
50 msg->falcon_id, name, msg->error_code); in gp102_sec2_acr_bootstrap_falcon_callback()
51 return -EINVAL; in gp102_sec2_acr_bootstrap_falcon_callback()
64 .cmd.hdr.unit_id = sec2->func->unit_acr, in gp102_sec2_acr_bootstrap_falcon()
71 return nvkm_falcon_cmdq_send(sec2->cmdq, &cmd.cmd.hdr, in gp102_sec2_acr_bootstrap_falcon()
73 &sec2->engine.subdev, in gp102_sec2_acr_bootstrap_falcon()
78 gp102_sec2_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gp102_sec2_acr_bld_patch() argument
[all …]
/linux/drivers/net/ethernet/atheros/atl1e/
H A Datl1e_param.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
13 /* This is the only thing that needs to be changed to adjust the
19 #define OPTION_UNSET -1
37 * Valid Range: 64-2048
48 * Valid Range: 16-512
59 * Valid Range: 0-5
60 * - 0 - auto-negotiate at all supported speeds
61 * - 1 - only link at 100Mbps Full Duplex
62 * - 2 - only link at 100Mbps Half Duplex
[all …]
/linux/fs/smb/smbdirect/
H A Daccept.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 struct smbdirect_socket_parameters *sp = &sc->parameters; in smbdirect_accept_connect_request()
30 return -EINVAL; in smbdirect_accept_connect_request()
35 sp->initiator_depth = min_t(u8, sp->initiator_depth, in smbdirect_accept_connect_request()
36 sc->ib.dev->attrs.max_qp_rd_atom); in smbdirect_accept_connect_request()
38 peer_initiator_depth = param->initiator_depth; in smbdirect_accept_connect_request()
39 peer_responder_resources = param->responder_resources; in smbdirect_accept_connect_request()
71 ret = -EINVAL; in smbdirect_accept_connect_request()
77 recv_io->cqe.done = smbdirect_accept_negotiate_recv_done; in smbdirect_accept_connect_request()
83 sc->recv_io.expected = SMBDIRECT_EXPECT_NEGOTIATE_REQ; in smbdirect_accept_connect_request()
[all …]
/linux/drivers/net/ethernet/intel/libeth/
H A Dxdp.c1 // SPDX-License-Identifier: GPL-2.0-only
22 spin_lock_init(&lock->lock); in __libeth_xdpsq_get()
23 lock->share = true; in __libeth_xdpsq_get()
41 lock->share = false; in __libeth_xdpsq_put()
45 void __acquires(&lock->lock)
48 spin_lock(&lock->lock); in __libeth_xdpsq_lock()
52 void __releases(&lock->lock)
55 spin_unlock(&lock->lock); in __libeth_xdpsq_unlock()
59 /* XDPSQ clean-up timers */
62 * libeth_xdpsq_init_timer - initialize an XDPSQ clean-up timer
[all …]
/linux/net/sctp/
H A Dtransport.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 1999-2000 Cisco, Inc.
4 * Copyright (c) 1999-2001 Motorola, Inc.
5 * Copyright (c) 2001-2003 International Business Machines Corp.
17 * lksctp developers <linux-sctp@vger.kernel.org>
46 peer->af_specific = sctp_get_af_specific(addr->sa.sa_family); in sctp_transport_init()
47 memcpy(&peer->ipaddr, addr, peer->af_specific->sockaddr_len); in sctp_transport_init()
48 memset(&peer->saddr, 0, sizeof(union sctp_addr)); in sctp_transport_init()
50 peer->sack_generation = 0; in sctp_transport_init()
58 peer->rto = msecs_to_jiffies(net->sctp.rto_initial); in sctp_transport_init()
[all …]
/linux/net/tipc/
H A Ddiscover.c4 * Copyright (c) 2003-2006, 2014-2018, Ericsson AB
5 * Copyright (c) 2005-2006, 2010-2011, Wind River Systems
47 /* indicates no timer in use */
51 * struct tipc_discoverer - information about an ongoing link setup request
59 * @timer: timer governing period between requests
71 struct timer_list timer;
77 * tipc_disc_init_msg - initializ
70 struct timer_list timer; global() member
[all...]
/linux/arch/arm/mach-omap2/
H A Dsram242x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mach-omap2/sram242x.S
9 * Richard Woodruff <r-woodruff2@ti.com>
31 stmfd sp!, {r0 - r12, lr} @ save registers on stack
39 str r3, [r2] @ go to L1-freq operation
62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
82 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
111 ldr r7, [r3] @ get timer value
[all …]
H A Dsram243x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mach-omap2/sram243x.S
9 * Richard Woodruff <r-woodruff2@ti.com>
31 stmfd sp!, {r0 - r12, lr} @ save registers on stack
39 str r3, [r2] @ go to L1-freq operation
62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
82 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
111 ldr r7, [r3] @ get timer value
[all …]
/linux/drivers/s390/cio/
H A Deadm_sch.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/timer.h>
55 orb->eadm.compat1 = 1; in orb_init()
56 orb->eadm.compat2 = 1; in orb_init()
57 orb->eadm.fmt = 1; in orb_init()
58 orb->eadm.x = 1; in orb_init()
63 union orb *orb = &get_eadm_private(sch)->orb; in eadm_subchannel_start()
67 orb->eadm.aob = virt_to_dma32(aob); in eadm_subchannel_start()
68 orb->eadm.intparm = (u32)virt_to_phys(sch); in eadm_subchannel_start()
69 orb->eadm.key = PAGE_DEFAULT_KEY >> 4; in eadm_subchannel_start()
[all …]
/linux/arch/m68k/atari/
H A Dtime.c6 * Assembled of parts of former atari/config.c 97-12-18 by Roman Hodek
63 /* set Timer C data Register */ in atari_sched_init()
65 /* start timer C, div = 1:100 */ in atari_sched_init()
67 /* install interrupt service routine for MFP Timer C */ in atari_sched_init()
68 if (request_irq(IRQ_MFP_TIMC, mfp_timer_c_handler, IRQF_TIMER, "timer", in atari_sched_init()
70 pr_err("Couldn't register timer interrupt\n"); in atari_sched_init()
85 * the result may briefly stop changing after counter wrap-around. in atari_read_clk()
90 ticks = INT_TICKS - count; in atari_read_clk()
100 #define COPY(v) val->v=(mste_rtc.v & 0xf) in mste_read()
108 } while (val->sec_ones != (mste_rtc.sec_ones & 0xf)); in mste_read()
[all …]

12345678