1 // SPDX-License-Identifier: GPL-2.0-only
59  * To get the value from the Global Timer Counter register proceed as follows:
60  * 1. Read the upper 32-bit timer counter register
61  * 2. Read the lower 32-bit timer counter register
62  * 3. Read the upper 32-bit timer counter register again. If the value is
63  *  different to the 32-bit upper value read previously, go back to step 2.
64  *  Otherwise the 64-bit timer counter value is correct.
93  * 1. Clear the Comp Enable bit in the Timer Control Register.
94  * 2. Write the lower 32-bit Comparator Value Register.
95  * 3. Write the upper 32-bit Comparator Value Register.
154 	 * ERRATA 740657( Global Timer can send 2 interrupts for  in gt_clockevent_interrupt()
155 	 * the same event in single-shot mode)  in gt_clockevent_interrupt()
157 	 *	Either disable single-shot mode.  in gt_clockevent_interrupt()
161 	 *	the Global Timer flag _after_ having incremented  in gt_clockevent_interrupt()
168 	evt->event_handler(evt);  in gt_clockevent_interrupt()
177 	clk->name = "arm_global_timer";  in gt_starting_cpu()
178 	clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |  in gt_starting_cpu()
180 	clk->set_state_shutdown = gt_clockevent_shutdown;  in gt_starting_cpu()
181 	clk->set_state_periodic = gt_clockevent_set_periodic;  in gt_starting_cpu()
182 	clk->set_state_oneshot = gt_clockevent_shutdown;  in gt_starting_cpu()
183 	clk->set_state_oneshot_stopped = gt_clockevent_shutdown;  in gt_starting_cpu()
184 	clk->set_next_event = gt_clockevent_set_next_event;  in gt_starting_cpu()
185 	clk->cpumask = cpumask_of(cpu);  in gt_starting_cpu()
186 	clk->rating = 300;  in gt_starting_cpu()
187 	clk->irq = gt_ppi;  in gt_starting_cpu()
190 	enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);  in gt_starting_cpu()
198 	disable_percpu_irq(clk->irq);  in gt_dying_cpu()
213 		/* re-enable timer on resume */  in gt_resume()
271 	/* set prescaler and enable timer on all the cores */  in gt_clocksource_init()
272 	writel(FIELD_PREP(GT_CONTROL_PRESCALER_MASK, psv - 1) |  in gt_clocksource_init()
291 		psv = DIV_ROUND_CLOSEST(ndata->new_rate, gt_target_rate);  in gt_clk_rate_change_cb()
293 		    abs(gt_target_rate - (ndata->new_rate / psv)) > MAX_F_ERR)  in gt_clk_rate_change_cb()
296 		psv--;  in gt_clk_rate_change_cb()
303 		 * store timer clock ctrl register so we can restore it in case  in gt_clk_rate_change_cb()
308 		/* scale down: adjust divider in post-change notification */  in gt_clk_rate_change_cb()
309 		if (ndata->new_rate < ndata->old_rate)  in gt_clk_rate_change_cb()
312 		/* scale up: adjust divider now - before frequency change */  in gt_clk_rate_change_cb()
317 		/* scale up: pre-change notification did the adjustment */  in gt_clk_rate_change_cb()
318 		if (ndata->new_rate > ndata->old_rate)  in gt_clk_rate_change_cb()
321 		/* scale down: adjust divider now - after frequency change */  in gt_clk_rate_change_cb()
327 		if (ndata->new_rate < ndata->old_rate)  in gt_clk_rate_change_cb()
347 	 * On am43 the global timer clock is a child of the clock used for CPU
354 	{ .compatible = "xlnx,zynq-7000", .prescaler = 2 },
365 	for (config = gt_prescaler_configs; config->compatible; config++) {  in gt_get_initial_prescaler_value()
366 		if (of_machine_is_compatible(config->compatible))  in gt_get_initial_prescaler_value()
367 			return config->prescaler;  in gt_get_initial_prescaler_value()
381 	 * In A9 r2p0 the comparators for each processor with the global timer  in global_timer_of_register()
382 	 * fire when the timer value is greater than or equal to. In previous  in global_timer_of_register()
383 	 * revisions the comparators fired when the timer value was equal to.  in global_timer_of_register()
387 		pr_warn("global-timer: non support for this cpu version.\n");  in global_timer_of_register()
388 		return -ENOSYS;  in global_timer_of_register()
393 		pr_warn("global-timer: unable to parse irq\n");  in global_timer_of_register()
394 		return -EINVAL;  in global_timer_of_register()
399 		pr_warn("global-timer: invalid base address\n");  in global_timer_of_register()
400 		return -ENXIO;  in global_timer_of_register()
409 		pr_warn("global-timer: clk not found\n");  in global_timer_of_register()
410 		err = -EINVAL;  in global_timer_of_register()
427 		pr_warn("global-timer: can't allocate memory\n");  in global_timer_of_register()
428 		err = -ENOMEM;  in global_timer_of_register()
435 		pr_warn("global-timer: can't register interrupt %d (%d)\n",  in global_timer_of_register()
440 	/* Register and immediately configure the timer on the boot CPU */  in global_timer_of_register()
465 	WARN(err, "ARM Global timer register failed (%d)\n", err);  in global_timer_of_register()
471 TIMER_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",