Home
last modified time | relevance | path

Searched +full:tegra30 +full:- +full:mc (Results 1 – 25 of 25) sorted by relevance

/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
13 compatible = "nvidia,tegra30";
[all …]
H A Dtegra124.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra124-peripherals-opp.dtsi"
[all …]
/linux/Documentation/devicetree/bindings/devfreq/
H A Dnvidia,tegra30-actmon.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/devfreq/nvidia,tegra30-actmon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra30 Activity Monitor
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
23 - nvidia,tegra30-actmon
24 - nvidia,tegra114-actmon
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra30-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra30 SoC Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 Tegra30 Memory Controller architecturally consists of the following parts:
33 The Tegra30 Memory Controller handles memory requests from internal clients
[all …]
H A Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra30 SoC External Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
[all …]
/linux/drivers/memory/tegra/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 tegra-mc-y := mc.o
4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o
5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
10 tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
11 tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra194.o
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
8 This driver supports the Memory Controller (MC) hardware found on
27 tristate "NVIDIA Tegra30 External Memory Controller driver"
34 Tegra30 chips. The EMC controls the external DRAM on the board.
H A Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Tegra30 External Memory Controller driver
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
18 #include <linux/interconnect-provider.h>
38 #include "mc.h"
357 struct tegra_mc *mc; member
392 /* protect shared rate-change code path */
403 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
[all …]
H A Dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/dma-mapping.h>
18 #include <linux/tegra-icc.h>
22 #include "mc.h"
26 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
29 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
32 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
35 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
38 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
[all …]
H A Dtegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/memory/tegra30-mc.h>
12 #include "mc.h"
1219 static void tegra30_mc_tune_client_latency(struct tegra_mc *mc, in tegra30_mc_tune_client_latency() argument
1224 unsigned int fifo_size = client->fifo_size; in tegra30_mc_tune_client_latency()
1244 switch (client->swgroup) { in tegra30_mc_tune_client_latency()
1271 arb_nsec -= arb_tolerance_compensation_nsec; in tegra30_mc_tune_client_latency()
1279 * client may wait in the EMEM arbiter before it becomes a high-priority in tegra30_mc_tune_client_latency()
1282 la_ticks = arb_nsec / mc->tick; in tegra30_mc_tune_client_latency()
1283 la_ticks = min(la_ticks, client->regs.la.mask); in tegra30_mc_tune_client_latency()
[all …]
/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-gr3d.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr3d.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^gr3d@[0-9a-f]+$"
19 - nvidia,tegra20-gr3d
20 - nvidia,tegra30-gr3d
21 - nvidia,tegra114-gr3d
[all …]
H A Dnvidia,tegra20-gr2d.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr2d.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^gr2d@[0-9a-f]+$"
19 - nvidia,tegra20-gr2d
20 - nvidia,tegra30-gr2d
21 - nvidia,tegra114-gr2d
[all …]
H A Dnvidia,tegra20-host1x.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The host1x top-level node defines a number of children, each
19 - enum:
20 - nvidia,tegra20-host1x
21 - nvidia,tegra30-host1x
[all …]
/linux/Documentation/devicetree/bindings/iommu/
H A Dnvidia,tegra30-smmu.txt4 - compatible : "nvidia,tegra30-smmu"
5 - reg : Should contain 3 register banks(address and length) for each
7 - interrupts : Should contain MC General interrupt.
8 - nvidia,#asids : # of ASIDs
9 - dma-window : IOVA start address and length.
10 - nvidia,ahb : phandle to the ahb bus connected to SMMU.
14 compatible = "nvidia,tegra30-smmu";
19 dma-window = <0 0x40000000>; /* IOVA start & length */
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra132-peripherals-opp.dtsi"
[all …]
H A Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
[all …]
H A Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
[all …]
/linux/drivers/gpu/drm/tegra/
H A Dgr3d.c1 // SPDX-License-Identifier: GPL-2.0-only
62 struct drm_device *dev = dev_get_drvdata(client->host); in gr3d_init()
67 gr3d->channel = host1x_channel_request(client); in gr3d_init()
68 if (!gr3d->channel) in gr3d_init()
69 return -ENOMEM; in gr3d_init()
71 client->syncpts[0] = host1x_syncpt_request(client, flags); in gr3d_init()
72 if (!client->syncpts[0]) { in gr3d_init()
73 err = -ENOMEM; in gr3d_init()
74 dev_err(client->dev, "failed to request syncpoint: %d\n", err); in gr3d_init()
80 dev_err(client->dev, "failed to attach to domain: %d\n", err); in gr3d_init()
[all …]
H A Dgr2d.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2013, NVIDIA Corporation.
52 struct drm_device *dev = dev_get_drvdata(client->host); in gr2d_init()
57 gr2d->channel = host1x_channel_request(client); in gr2d_init()
58 if (!gr2d->channel) in gr2d_init()
59 return -ENOMEM; in gr2d_init()
61 client->syncpts[0] = host1x_syncpt_request(client, flags); in gr2d_init()
62 if (!client->syncpts[0]) { in gr2d_init()
63 err = -ENOMEM; in gr2d_init()
64 dev_err(client->dev, "failed to request syncpoint: %d\n", err); in gr2d_init()
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dnvidia,tegra-vde.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
19 - nvidia,tegra132-vde
[all …]
/linux/drivers/clk/tegra/
H A Dclk-tegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/tegra30-car.h>
21 #include "clk-id.h"
596 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
597 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
598 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
602 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
603 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
605 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
[all …]
/linux/Documentation/devicetree/bindings/serial/
H A D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
[all …]
/linux/drivers/iommu/
H A Dtegra-smmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved.
17 #include <linux/dma-mapping.h>
20 #include <soc/tegra/mc.h>
22 #include "iommu-pages.h"
36 struct tegra_mc *mc; member
78 writel(value, smmu->regs + offset); in smmu_writel()
83 return readl(smmu->regs + offset); in smmu_readl()
93 ((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask)
125 /* per-SWGROUP SMMU_*_ASID register */
[all …]
/linux/drivers/gpu/host1x/
H A Ddev.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
10 #include <linux/dma-mapping.h>
27 #include <asm/dma-iommu.h>
47 writel(v, host1x->common_regs + r); in host1x_common_writel()
52 writel(v, host1x->hv_regs + r); in host1x_hypervisor_writel()
57 return readl(host1x->hv_regs + r); in host1x_hypervisor_readl()
62 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; in host1x_sync_writel()
69 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; in host1x_sync_readl()
76 writel(v, ch->regs + r); in host1x_ch_writel()
[all …]
/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
[all …]