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Searched +full:tegra210 +full:- +full:qspi (Results 1 – 10 of 10) sorted by relevance

/linux/Documentation/devicetree/bindings/spi/
H A Dnvidia,tegra210-quad.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra210-qspi
17 - nvidia,tegra186-qspi
18 - nvidia,tegra194-qspi
19 - nvidia,tegra234-qspi
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H A Dnvidia,tegra210-quad-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 nvidia,tx-clk-tap-delay:
18 QSPI to corresponding slave device.
23 nvidia,rx-clk-tap-delay:
27 QSPI to corresponding slave device.
H A Dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cs-high, etc. or they could
14 per-peripheral and there can be multiple peripherals attached to a
20 - Mark Brown <broonie@kernel.org>
28 - minimum: 0
33 spi-cs-high:
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra210-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra210-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 Pinmux Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra210-pinmux
19 - description: APB_MISC_GP_*_PADCTRL register (pad control)
20 - description: PINMUX_AUX_* registers (pinmux)
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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/linux/drivers/spi/
H A Dspi-tegra210-quad.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
243 return readl(tqspi->base + offset); in tegra_qspi_readl()
248 writel(value, tqspi->base + offset); in tegra_qspi_writel()
252 readl(tqspi->base + QSPI_COMMAND1); in tegra_qspi_writel()
279 unsigned int remain_len = t->len - tqspi->cur_pos; in tegra_qspi_calculate_curr_xfer_param()
280 unsigned int bits_per_word = t->bits_per_word; in tegra_qspi_calculate_curr_xfer_param()
282 tqspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); in tegra_qspi_calculate_curr_xfer_param()
285 * Tegra QSPI controller supports packed or unpacked mode transfers. in tegra_qspi_calculate_curr_xfer_param()
292 bits_per_word == 32) && t->len > 3) { in tegra_qspi_calculate_curr_xfer_param()
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/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Pinctrl data for the NVIDIA Tegra210 pinmux
14 #include "pinctrl-tegra.h"
177 /* All non-GPIO pins follow */
181 /* Non-GPIO pins */
1231 FUNCTION(qspi),
1269 #define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
1270 #define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
1273 #define PINGROUP_BIT_N(b) (-1)
1300 .ioreset_bit = -1, \
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/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-id.h"
130 #define MASK(x) (BIT(x) - 1)
761 …MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, …
787 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
873 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in periph_clk_init()
877 bank = get_reg_bank(data->periph.gate.clk_num); in periph_clk_init()
881 data->periph.gate.regs = bank; in periph_clk_init()
899 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in gate_clk_init()
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