| /linux/Documentation/devicetree/bindings/mfd/ |
| H A D | qcom,tcsr.yaml | 4 $id: http://devicetree.org/schemas/mfd/qcom,tcsr.yaml#
20 - qcom,msm8976-tcsr
21 - qcom,msm8998-tcsr
22 - qcom,qcm2290-tcsr
23 - qcom,qcs404-tcsr
24 - qcom,qcs615-tcsr
25 - qcom,qcs8300-tcsr
26 - qcom,sa8255p-tcsr
27 - qcom,sa8775p-tcsr
28 - qcom,sc7180-tcsr
[all …]
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | qcom,sm8550-tcsr.yaml | 4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml#
7 title: Qualcomm TCSR Clock Controller on SM8550
14 Qualcomm TCSR clock control module provides the clocks, resets and
18 - include/dt-bindings/clock/qcom,glymur-tcsr.h
19 - include/dt-bindings/clock/qcom,sm8550-tcsr.h
20 - include/dt-bindings/clock/qcom,sm8650-tcsr.h
21 - include/dt-bindings/clock/qcom,sm8750-tcsr.h
27 - qcom,glymur-tcsr
28 - qcom,kaanapali-tcsr
29 - qcom,milos-tcsr
[all …]
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| /linux/Documentation/devicetree/bindings/hwlock/ |
| H A D | qcom-hwspinlock.yaml | 21 - qcom,tcsr-mutex
24 - qcom,apq8084-tcsr-mutex
25 - qcom,ipq6018-tcsr-mutex
26 - qcom,msm8226-tcsr-mutex
27 - qcom,msm8994-tcsr-mutex
28 - const: qcom,tcsr-mutex
31 - qcom,msm8974-tcsr-mutex
32 - const: qcom,tcsr-mutex
51 compatible = "qcom,tcsr-mutex";
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| /linux/drivers/soc/qcom/ |
| H A D | qcom_gsbi.c | 114 struct regmap *tcsr; member
118 { .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064},
119 { .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064},
120 { .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960},
121 { .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660},
145 /* get the tcsr node and setup the config and regmap */ in gsbi_probe()
146 gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr"); in gsbi_probe()
148 if (!IS_ERR(gsbi->tcsr)) { in gsbi_probe()
149 tcsr_node = of_parse_phandle(node, "syscon-tcsr", 0); in gsbi_probe()
155 dev_warn(&pdev->dev, "no matching TCSR\n"); in gsbi_probe()
[all …]
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| /linux/include/clocksource/ |
| H A D | timer-xilinx.h | 51 * @tcsr: The value of the TCSR register for this counter
59 u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr,
66 * @tcsr: The value of TCSR for this counter
71 u32 tlr, u32 tcsr);
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| /linux/drivers/hwspinlock/ |
| H A D | qcom_hwspinlock.c | 141 { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex },
142 { .compatible = "qcom,apq8084-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
143 { .compatible = "qcom,msm8226-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
144 { .compatible = "qcom,msm8974-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
145 { .compatible = "qcom,msm8994-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
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| /linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-qusb2.c | 289 /* offset to PHY_CLK_SCHEME register in TCSR map */
442 * @tcsr: TCSR syscon register map
462 struct regmap *tcsr; member
820 * register in the TCSR so, if there's none, use the default in qusb2_phy_init()
831 if (qphy->tcsr) { in qusb2_phy_init()
832 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, in qusb2_phy_init()
1039 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, in qusb2_phy_probe()
1040 "qcom,tcsr-syscon"); in qusb2_phy_probe()
1041 if (IS_ERR(qphy->tcsr)) { in qusb2_phy_probe()
1042 dev_dbg(dev, "failed to lookup TCSR regmap\n"); in qusb2_phy_probe()
[all …]
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| /linux/drivers/clk/qcom/ |
| H A D | tcsrcc-sm8550.c | 14 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
169 { .compatible = "qcom,sar2130p-tcsr", .data = &tcsr_cc_sar2130p_desc },
170 { .compatible = "qcom,sm8550-tcsr", .data = &tcsr_cc_sm8550_desc },
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| H A D | tcsrcc-x1e80100.c | 13 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
258 { .compatible = "qcom,x1e80100-tcsr" },
288 MODULE_DESCRIPTION("QTI TCSR Clock Controller X1E80100 Driver");
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| H A D | Kconfig | 42 tristate "GLYMUR TCSR Clock Controller"
46 Support for the TCSR clock controller on GLYMUR devices.
87 tristate "X1E80100 TCSR Clock Controller"
91 Support for the TCSR clock controller on X1E80100 devices.
1429 tristate "SM8550 TCSR Clock Controller"
1433 Support for the TCSR clock controller on SM8550 devices.
1437 tristate "SM8650 TCSR Clock Controller"
1441 Support for the TCSR clock controller on SM8650 devices.
1445 tristate "SM8750 TCSR Clock Controller"
1449 Support for the TCSR clock controller on SM8750 devices.
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| H A D | tcsrcc-glymur.c | 13 #include <dt-bindings/clock/qcom,glymur-tcsr.h>
282 { .compatible = "qcom,glymur-tcsr" },
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| /linux/drivers/pwm/ |
| H A D | pwm-xilinx.c | 34 u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr, in xilinx_timer_tlr_cycles() argument
39 if (tcsr & TCSR_UDT) in xilinx_timer_tlr_cycles()
45 u32 tlr, u32 tcsr) in xilinx_timer_get_period() argument
49 if (tcsr & TCSR_UDT) in xilinx_timer_get_period()
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| /linux/drivers/pmdomain/qcom/ |
| H A D | cpr.c | 237 struct regmap *tcsr; member
393 static void cpr_set_acc(struct regmap *tcsr, struct fuse_corner *f, in cpr_set_acc() argument
401 regmap_multi_reg_write(tcsr, f->accs, f->num_accs); in cpr_set_acc()
404 regmap_multi_reg_write(tcsr, f->accs, f->num_accs); in cpr_set_acc()
414 if (drv->tcsr && dir == DOWN) in cpr_pre_voltage()
415 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); in cpr_pre_voltage()
426 if (drv->tcsr && dir == UP) in cpr_post_voltage()
427 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); in cpr_post_voltage()
1517 regmap_multi_reg_write(drv->tcsr, acc_desc->config, in cpr_pd_attach_dev()
1522 regmap_update_bits(drv->tcsr, acc_desc->enable_reg, in cpr_pd_attach_dev()
[all …]
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| /linux/Documentation/arch/mips/ |
| H A D | ingenic-tcu.rst | 19 different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
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| /linux/arch/arm/boot/dts/qcom/ |
| H A D | qcom-msm8960.dtsi | 585 syscon-tcsr = <&tcsr>;
612 syscon-tcsr = <&tcsr>;
677 tcsr: syscon@1a400000 { label
678 compatible = "qcom,tcsr-msm8960", "syscon";
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | ci-hdrc-usb2.yaml | 60 Phandler of TCSR node with two argument that indicate register
64 - description: phandle to TCSR node
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| /linux/drivers/net/ethernet/marvell/mvpp2/ |
| H A D | mvpp2_tai.c | 242 u32 tcsr; in mvpp22_tai_gettimex64() local
260 tcsr = readl(base + MVPP22_TAI_TCSR); in mvpp22_tai_gettimex64()
261 if (tcsr & TCSR_CAPTURE_1_VALID) { in mvpp22_tai_gettimex64()
264 } else if (tcsr & TCSR_CAPTURE_0_VALID) { in mvpp22_tai_gettimex64()
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| /linux/drivers/clk/ingenic/ |
| H A D | tcu.c | 130 WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx); in ingenic_tcu_get_parent()
146 WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx); in ingenic_tcu_set_parent()
163 WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx); in ingenic_tcu_recalc_rate()
212 WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx); in ingenic_tcu_set_rate()
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| /linux/Documentation/devicetree/bindings/ufs/ |
| H A D | qcom,sm8650-ufshc.yaml | 75 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
96 <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
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| /linux/Documentation/devicetree/bindings/firmware/ |
| H A D | qcom,scm.yaml | 123 - description: phandle to TCSR hardware block
125 description: TCSR hardware block
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| /linux/include/dt-bindings/clock/ |
| H A D | qcom,sc8280xp-lpasscc.h | 14 /* LPASS TCSR */
|
| H A D | qcom,sm8550-tcsr.h | 10 /* TCSR CC clocks */
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| H A D | qcom,sm8650-tcsr.h | 10 /* TCSR CC clocks */
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| H A D | qcom,x1e80100-tcsr.h | 9 /* TCSR CC clocks */
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| /linux/drivers/rtc/ |
| H A D | rtc-rs5c348.c | 101 udelay(62); /* Tcsr 62us */ in rs5c348_rtc_set_time()
133 udelay(62); /* Tcsr 62us */ in rs5c348_rtc_read_time()
|