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/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10_socdk_qspi.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
15 compatible = "micron,mt25qu02g", "jedec,spi-nor";
17 spi-max-frequency = <100000000>;
19 m25p,fast-read;
20 cdns,read-delay = <3>;
21 cdns,tshsl-ns = <50>;
22 cdns,tsd2d-ns = <50>;
[all …]
H A Dsocfpga_cyclone5_vining_fpga.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
12 compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
16 stdout-path = "serial0:115200n8";
34 gpio-keys {
35 compatible = "gpio-keys";
68 regulator-usb-nrst {
69 compatible = "regulator-fixed";
70 regulator-name = "usb_nrst";
[all …]
H A Dsocfpga_cyclone5_socrates.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
18 stdout-path = "serial0:115200n8";
27 leds: gpio-leds {
32 phy-mode = "rgmii";
54 compatible = "gpio-leds";
59 linux,default-trigger = "heartbeat";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 compatible = "micron,n25q256a", "jedec,spi-nor";
[all …]
H A Dsocfpga_cyclone5_mercury_sa1.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
10 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
13 stdout-path = "serial0:115200n8";
20 /* Adjusted the i2c labels to use generic base-board dtsi files for
24 * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi
26 * bus in a generic base-board .dtsi file.
43 clock-frequency = <50000000>;
47 i2c-sda-hold-time-ns = <300>;
48 clock-frequency = <100000>;
[all …]
H A Dsocfpga_cyclone5_mercury_sa2.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
10 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
13 stdout-path = "serial0:115200n8";
20 /* Adjusted the i2c labels to use generic base-board dtsi files for
24 * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi
26 * bus in a generic base-board .dtsi file.
43 clock-frequency = <50000000>;
47 i2c-sda-hold-time-ns = <300>;
48 clock-frequency = <100000>;
[all …]
H A Dsocfpga_cyclone5_sodia.dts1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
12 compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga";
16 stdout-path = "serial0:115200n8";
30 compatible = "regulator-fixed";
31 regulator-name = "3.3V";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
36 leds: gpio-leds {
[all …]
H A Dsocfpga_arria5_socdk.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "altr,socfpga-arria5-socdk", "altr,socfpga-arria5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
32 led-hps0 {
37 led-hps1 {
42 led-hps2 {
47 led-hps3 {
54 compatible = "regulator-fixed";
55 regulator-name = "3.3V";
[all …]
H A Dsocfpga_arria10_mercury_aa1.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 compatible = "enclustra,mercury-aa1",
12 "altr,socfpga-arria10", "altr,socfpga";
27 stdout-path = "serial1:115200n8";
30 /* Adjusted the i2c labels to use generic base-board dtsi files for
34 * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi
36 * bus in a generic base-board .dtsi file.
48 i2c-sda-hold-time-ns = <300>;
49 clock-frequency = <100000>;
63 i2c-sda-hold-time-ns = <300>;
[all …]
H A Dsocfpga_cyclone5_sockit.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
36 linux,default-trigger = "heartbeat";
42 linux,default-trigger = "heartbeat";
48 linux,default-trigger = "heartbeat";
54 linux,default-trigger = "heartbeat";
58 gpio-keys {
59 compatible = "gpio-keys";
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dcdns,qspi-nor-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for the Cadence QSPI controller.
10 See spi-peripheral-props.yaml for more info.
13 - Vaishnav Achath <vaishnav.a@ti.com>
16 # cdns,qspi-nor.yaml
17 cdns,read-delay:
22 cdns,tshsl-ns:
[all …]
/linux/arch/arm64/boot/dts/amd/
H A Delba-asic-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2022 Advanced Micro Devices, Inc.
7 clock-frequency = <400000000>;
11 clock-frequency = <200000000>;
15 clock-frequency = <400000000>;
19 clock-frequency = <156250000>;
26 compatible = "jedec,spi-nor";
28 spi-max-frequency = <40000000>;
29 spi-rx-bus-width = <2>;
30 m25p,fast-read;
[all …]
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5_socdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5";
19 stdout-path = "serial0:115200n8";
23 compatible = "gpio-leds";
25 led-0 {
45 phy-mode = "rgmii-id";
46 phy-handle = <&emac2_phy0>;
47 max-frame-size = <9000>;
50 #address-cells = <1>;
51 #size-cells = <0>;
[all …]
H A Dsocfpga_agilex3_socdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 compatible = "intel,socfpga-agilex3-socdk", "intel,socfpga-agilex3",
10 "intel,socfpga-agilex5";
18 stdout-path = "serial0:115200n8";
22 /delete-node/ cpu@2;
23 /delete-node/ cpu@3;
27 compatible = "gpio-leds";
50 phy-mode = "rgmii-id";
51 phy-handle = <&emac2_phy0>;
52 max-frame-size = <9000>;
[all …]
H A Dsocfpga_agilex5_socdk_013b.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 compatible = "intel,socfpga-agilex5-socdk-013b", "intel,socfpga-agilex5";
17 stdout-path = "serial0:115200n8";
21 compatible = "gpio-leds";
44 phy-mode = "rgmii-id";
45 phy-handle = <&emac2_phy0>;
46 max-frame-size = <9000>;
49 #address-cells = <1>;
50 #size-cells = <0>;
51 compatible = "snps,dwmac-mdio";
[all …]
H A Dsocfpga_n5x_socdk.dts1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "intel,n5x-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
29 sdram_edac: memory-controller@f87f8000 {
30 compatible = "snps,ddrc-3.80a";
38 compatible = "intel,easic-n5x-clkmgr";
43 phy-mode = "rgmii";
44 phy-handle = <&phy0>;
46 max-frame-size = <9000>;
49 #address-cells = <1>;
[all …]
H A Dsocfpga_agilex_socdk.dts1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
23 compatible = "gpio-leds";
53 phy-mode = "rgmii";
54 phy-handle = <&phy0>;
56 max-frame-size = <9000>;
59 #address-cells = <1>;
60 #size-cells = <0>;
61 compatible = "snps,dwmac-mdio";
[all …]
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10_socdk_nand.dts1 // SPDX-License-Identifier: GPL-2.0-only
10 compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
25 led-hps0 {
30 led-hps1 {
35 led-hps2 {
47 ref_033v: regulator-v-ref {
48 compatible = "regulator-fixed";
49 regulator-name = "0.33V";
[all …]
H A Dsocfpga_stratix10_socdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
10 compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
25 led-hps0 {
30 led-hps1 {
35 led-hps2 {
47 ref_033v: regulator-v-ref {
48 compatible = "regulator-fixed";
49 regulator-name = "0.33V";
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am642-tqma64xxl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 * Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
7 #include "k3-am642.dtsi"
18 /* 1G RAM - default variant */
20 bootph-pre-ram;
23 reserved_memory: reserved-memory {
24 #address-cells = <2>;
25 #size-cells = <2>;
31 no-map;
[all …]
H A Dk3-am625-sk-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-am62x-sk-common.dtsi"
11 opp-table {
12 /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
13 opp-1400000000 {
14 opp-hz = /bits/ 64 <1400000000>;
15 opp-supported-hw = <0x01 0x0004>;
16 clock-latency-ns = <6000000>;
20 vmain_pd: regulator-0 {
[all …]
H A Dk3-am69-aquila-clover.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69
6 * https://www.toradex.com/products/carrier-board/clover
9 /dts-v1/;
11 #include <dt-bindings/pwm/pwm.h>
12 #include "k3-am69-aquila.dtsi"
16 compatible = "toradex,aquila-am69-clover",
17 "toradex,aquila-am69",
24 reg_3v3_dp: regulator-3v3-dp {
25 compatible = "regulator-fixed";
[all …]
H A Dk3-am64-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com
6 * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
10 * https://www.phytec.com/product/phycore-am64x
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/net/ti-dp83867.h>
18 model = "PHYTEC phyCORE-AM64x";
19 compatible = "phytec,am64-phycore-som", "ti,am642";
30 bootph-all;
[all …]
H A Dk3-am68-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
6 * https://www.phytec.eu/en/produkte/system-on-modules/phycore-am68x-tda4x/
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-j721s2.dtsi"
16 compatible = "phytec,am68-phycore-som", "ti,j721s2";
17 model = "PHYTEC phyCORE-AM68x";
30 bootph-all;
33 reserved_memory: reserved-memory {
[all …]
H A Dk3-am62a-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2023 - 2024 PHYTEC America LLC
7 * https://www.phytec.com/product/phycore-am62a
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
15 model = "PHYTEC phyCORE-AM62Ax";
16 compatible = "phytec,am62a-phycore-som", "ti,am62a7";
29 compatible = "gpio-leds";
30 pinctrl-names = "default";
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-common.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include "jh7110-pinfunc.h"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
27 stdout-path = "serial0:115200n8";
33 bootph-pre-ram;
36 gpio-restart {
37 compatible = "gpio-restart";
[all …]

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