| /freebsd/share/man/man4/ |
| H A D | acpi_hp.4 | 15 .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 .Bd -ragged -offset indent
39 Alternatively, to load the driver as a
42 .Bd -literal -offset indent
48 driver provides support for ACPI-controlled features found on HP laptops
49 that use a WMI enabled BIOS (e.g., HP Compaq 8510p and 6510p).
63 .Bl -tag -width "subsystem" -offset indent -compact
64 .It system
70 The value depends on the model.
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| H A D | ahc.4 | 18 .\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 .\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 .Bd -ragged -offset indent
45 Alternatively, to load the driver as a
48 .Bd -literal -offset indent
60 fast, ultra or ultra2 synchronous transfers depending on controller type,
64 .Tn SCSI-Select
72 For systems that store non-volatile settings in a system specific manner
73 rather than a serial eeprom directly connected to the aic7xxx controller,
78 many chip-down motherboard configurations.
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| H A D | rl.4 | 15 .\" 4. Neither the name of the author nor the names of any co-contributors
21 .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 .\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
41 .Bd -ragged -offset indent
46 Alternatively, to load the driver as a
49 .Bd -literal -offset indent
56 controllers based on the RealTek 8129 and 8139 Fast Ethernet controller
59 The RealTek 8129/8139 series controllers use bus master DMA but do not use a
60 descriptor-based data transfer mechanism.
61 The receiver uses a
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| H A D | ltc430x.4 | 1 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
17 .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37 .Bd -ragged -offset indent
41 Alternatively, to load the driver as a
44 .Bd -literal -offset indent
52 buses as needed when slave devices on the downstream buses initiate I/O.
53 More information on the automatic switching behavior is available in
58 based system, an
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| H A D | spigen.4 | 17 .\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 .\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 .Bd -ragged -offset indent
42 Alternatively, to load the driver as a
45 .Bd -literal -offset indent
51 driver provides direct access to a slave device on the SPI bus.
52 Each instance of a
54 device is associated with a single chip-select
55 line on the bus, and all I/O performed through that instance is done
56 with that chip-select line asserted.
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| H A D | iicbus.4 | 15 .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 .Nd I2C bus system
41 system provides a uniform, modular and architecture-independent
42 system for the implementation of drivers to control various I2C devices
49 easy way to connect a CPU to peripheral chips in a TV-set.
51 The BUS physically consists of 2 active wires and a ground connection.
57 is a CPU, LCD driver, memory, or complex function chip.
59 can act as a receiver and/or transmitter depending on its functionality.
60 Obviously an LCD driver is only a receiver, while a memory or I/O chip can
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| H A D | mx25l.4 | 16 .\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 .\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 .Nd driver for SpiFlash(tm) compatible non-volatile storage devices
35 .Bd -ragged -offset indent
39 Alternatively, to load the driver as a
42 .Bd -literal -offset indent
48 driver provides support for the family of non-volatile storage
57 The device ID is looked up using a table of data within the driver
60 When a supported device is found, the
62 driver creates a disk device and makes it accessible at
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| H A D | at45d.4 | 16 .\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 .\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 .Nd driver for DataFlash(tm) non-volatile storage devices
35 .Bd -ragged -offset indent
39 Alternatively, to load the driver as a
42 .Bd -literal -offset indent
48 driver provides support for the family of non-volatile storage
60 The device ID is looked up using a table of data within the driver
63 When a supported device is found, the
65 driver creates a disk device and makes it accessible at
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| /freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/ |
| H A D | other.json | 11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong …
23 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data …
24 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…
36 … got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump w…
41 …"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a…
42 …urced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump w…
59 …"BriefDescription": "Initial and Final Pump Scope was system pump for all data types (demand load,…
60 …n": "Initial and Final Pump Scope and data sourced across this scope was system pump for all data …
65 …n": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) …
[all …]
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| H A D | frontend.json | 5 …"BriefDescription": "Branch instruction completed with a target address less than current instruct…
41 "BriefDescription": "Cycles when a demand ifetch was pending",
47 "BriefDescription": "Number of I-ERAT reloads",
53 "BriefDescription": "IERAT Reloaded (Miss) for a 16M page",
59 "BriefDescription": "IERAT Miss (Not implemented as DI on POWER6)",
60 "PublicDescription": "IERAT Reloaded (Miss) for a 4k page"
65 "BriefDescription": "IERAT Reloaded (Miss) for a 64k page",
71 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instru…
72 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…
89 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), …
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| /freebsd/lib/libpmc/pmu-events/arch/powerpc/power9/ |
| H A D | marked.json | 5 …"BriefDescription": "Number of cycles the marked instruction is experiencing a stall while it is n…
10 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond …
20 …BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another c…
25 …ocessor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) d…
30 …"BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or mem…
45 …"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's …
50 …"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's …
60 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due…
70 …iefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another cor…
85 …he processor's Instruction cache was reloaded from a location other than the local core's L3 due t…
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | syna.txt | 3 According to https://www.synaptics.com/company/news/conexant-marvell
7 ---------------------------------------------------------------
9 Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
18 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
20 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
26 model = "Sony NSZ-GS7";
27 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
34 CPU control register allows various operations on CPUs, like resetting them
38 - compatible: should be "marvell,berlin-cpu-ctrl"
39 - reg: address and length of the register set
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | pmc.txt | 4 - compatible: "fsl,<chip>-pmc".
6 "fsl,mpc8349-pmc" should be listed for any chip whose PMC is
7 compatible. "fsl,mpc8313-pmc" should also be listed for any chip
8 whose PMC is compatible, and implies deep-sleep capability.
10 "fsl,mpc8548-pmc" should be listed for any chip whose PMC is
11 compatible. "fsl,mpc8536-pmc" should also be listed for any chip
12 whose PMC is compatible, and implies deep-sleep capability.
14 "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
15 compatible; all statements below that apply to "fsl,mpc8548-pmc" also
16 apply to "fsl,mpc8641d-pmc".
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| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | jedec,spi-nor.txt | 4 - #address-cells, #size-cells : Must be present if the device has sub-nodes
6 - compatible : May include a device-specific string consisting of the
7 manufacturer and name of the chip. A list of supported chip
9 Must also include "jedec,spi-nor" for any SPI NOR flash that can
12 Supported chip names:
50 The following chip names have been used historically to
53 m25p05-nonjedec
54 m25p10-nonjedec
55 m25p20-nonjedec
56 m25p40-nonjedec
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr-channel.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR channel with chip/rank topology description
10 An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
11 CK, etc.) that connect one or more LPDDR chips to a host system. The main
12 purpose of this node is to overall LPDDR topology of the system, including the
13 amount of individual LPDDR chips and the ranks per chip.
16 - Julius Werner <jwerner@chromium.org>
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| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | socionext,uniphier-system-bus.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier System Bus
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
12 some control signals. It supports up to 8 banks (chip selects).
16 within each bank to the CPU-viewed address. The needed setup includes the
21 - Masahiro Yamada <yamada.masahiro@socionext.com>
[all …]
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| /freebsd/share/man/man4/man4.arm/ |
| H A D | imx6_snvs.4 | 17 .\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 .\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 .Nd device driver for the NXP i.MX6 on-chip Realtime Clock
36 .Bd -ragged -offset indent
40 Alternatively, to load the driver as a
43 .Bd -literal -offset indent
50 support for the i.MX6 on-chip realtime clock.
51 It provides the time of day with a resolution of approximately
55 stands for Secure Non-Volatile Storage, and refers to the subsystem
56 within the chip that (optionally) remains powered by a battery when
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| H A D | mge.4 | 17 .\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 .\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 .Bd -ragged -offset indent
43 system-on-chip devices.
48 .Bl -tag -width xxxxxxxxxxxxxxxxxxxx
62 .Bl -tag -width xxxxxxxxxxxxxxxxxxxx
63 .It full-duplex
69 driver supports polled operation when the system is configured with
89 driver supports interrupts coalescing (IC) so that raising a transmit/receive
90 frame interrupt is delayed, if possible, until a threshold-defined period of
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| H A D | imx_wdog.4 | 17 .\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 .\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 .Bd -ragged -offset indent
40 Alternatively, to load the driver as a
43 .Bd -literal -offset indent
51 support for the watchdog timer present on NXP i.MX5 and i.MX6 processors.
53 0.5 to 128 seconds, in half-second increments.
55 timeout period can be changed to any valid non-zero value.
57 At power-on, a special 16-second
58 .Sq power-down timer
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| /freebsd/sys/contrib/device-tree/Bindings/watchdog/ |
| H A D | aspeed-wdt.txt | 4 - compatible: must be one of:
5 - "aspeed,ast2400-wdt"
6 - "aspeed,ast2500-wdt"
7 - "aspeed,ast2600-wdt"
9 - reg: physical base address of the controller and length of memory mapped
14 - aspeed,reset-typ
[all...] |
| /freebsd/contrib/ntp/ntpd/ |
| H A D | ntpd-opts.def | 1 /* -*- Mode: Text -*- */
7 prog-name = "ntpd";
8 prog-title = "set clock via Network Time Protocol daemon";
11 #include ntpdbase-opts.def
14 explain = <<- _END_EXPLAIN
17 doc-section = {
18 ds-type = 'DESCRIPTION';
19 ds-format = 'mdoc';
20 ds-text = <<- _END_PROG_MDOC_DESCRIP
23 utility is an operating system daemon which sets
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| H A D | ntpd.1ntpdmdoc | 4 .\" EDIT THIS FILE WITH CAUTION (ntpd-opts.mdoc)
6 .\" It has been AutoGen-ed May 25, 2024 at 12:03:54 AM by AutoGen 5.18.16
7 .\" From the definitions ntpd-opts.def
8 .\" and the template file agmdoc-cmd.tpl
17 .Op Fl \-option\-name Ns Oo Oo Ns "=| " Oc Ns Ar value Oc
23 utility is an operating system daemon which sets
24 and maintains the system time of day in synchronism with Internet
26 It is a complete implementation of the
27 Network Time Protocol (NTP) version 4, as defined by RFC\-590
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-sprd-adi.txt | 3 ADI is the abbreviation of Anolog-Digital interface, which is used to access
4 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
9 48 hardware channels to access analog chip. For 2 software read/write channels,
10 users should set ADI registers to access analog chip. For hardware channels,
12 which means we can just link one analog chip address to one hardware channel,
13 then users can access the mapped analog chip address by this hardware channel
16 Thus we introduce one property named "sprd,hw-channels" to configure hardware
19 the analog chip address where user want to access by hardware components.
21 Since we have multi-subsystems will use unique ADI to access analog chip, when
22 one system is reading/writing data by ADI software channels, that should be under
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| /freebsd/contrib/ntp/html/ |
| H A D | clock.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
12 <!-- #BeginDate format:En2m -->4-Aug-2011 23:40<!-- #EndDate -->
16 <li class="inline"><a href="#intro">General Overview</a></li>
17 <li class="inline"><a href="#panic">Panic Threshold</a></li>
18 <li class="inline"><a href="#step">Step and Stepout Thresholds</a></li>
19 <li class="inline"><a href="#hold">Hold Timer</a></li>
20 <li class="inline"><a href="#inter">Operating Intervals</a></li>
21 <li class="inline"><a href="#state">State Transition Function</a></li>
25 … the NTPv4 specification and reference implementation a state machine is used to manage the system…
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| /freebsd/sys/contrib/device-tree/Bindings/rtc/ |
| H A D | isil,isl12057.txt | 1 Intersil ISL12057 I2C RTC/Alarm chip
3 ISL12057 is a trivial I2C device (it has simple device tree bindings,
4 consisting of a compatible field, an address and possibly an interrupt
8 ("wakeup-source") to handle the specific use-case found
9 on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104
10 and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
12 to the SoC but to a PMIC. It allows the device to be powered up when
13 RTC alarm rings. In order to mark the device has a wakeup source and
15 be set when the IRQ#2 pin of the chip is not connected to the SoC but
20 - "compatible": must be "isil,isl12057"
[all …]
|