Home
last modified time | relevance | path

Searched +full:system +full:- +full:clock +full:- +full:frequency (Results 1 – 25 of 789) sorted by relevance

12345678910>>...32

/linux/Documentation/timers/
H A Dtimekeeping.rst2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
22 Clock sources
23 -------------
25 The purpose of the clock source is to provide a timeline for the system that
[all …]
/linux/arch/sparc/include/asm/
H A Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
26 #define BBC_CSC 0x0d /* [B] Clock Synthesizers Control*/
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
33 #define BBC_ES_FSL 0x1c /* [W] E* Frequency Switch Latency*/
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
[all …]
/linux/arch/powerpc/include/asm/
H A Dmpc5121.h1 /* SPDX-License-Identifier: GPL-2.0-only */
23 * Clock Control Module
26 u32 spmr; /* System PLL Mode Register */
27 u32 sccr1; /* System Clock Control Register 1 */
28 u32 sccr2; /* System Clock Control Register 2 */
29 u32 scfr1; /* System Clock Frequency Register 1 */
30 u32 scfr2; /* System Clock Frequency Register 2 */
31 u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
33 u32 psc_ccr[12]; /* PSC Clock Control Registers */
34 u32 spccr; /* SPDIF Clock Control Register */
[all …]
/linux/drivers/net/ethernet/intel/e1000e/
H A Dptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
4 /* PTP 1588 Hardware Clock (PHC)
5 * Derived from PTP Hardware Clock driver for Intel 82576 and 82580 (igb)
18 * e1000e_phc_adjfine - adjust the frequency of the hardware clock
19 * @ptp: ptp clock structure
20 * @delta: Desired frequency chance in scaled parts per million
22 * Adjust the frequency of the PHC cycle counter by the indicated delta from
23 * the base frequency.
31 struct e1000_hw *hw = &adapter->hw; in e1000e_phc_adjfine()
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dnvidia,tegra124-car.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Clock and Reset Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The Clock and Reset (CAR) is the HW module responsible for muxing and gating
18 the clock source programming and most of the clock dividers.
20 CLKGEN input signals include the external clock for the reference frequency
[all …]
H A Drenesas,emev2-smu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas EMMA Mobile EV2 System Management Unit
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
14 The System Management Unit is described in user's manual R19UH0037EJ1000_SMU.
15 This is not a clock provider, but clocks under SMU depend on it.
19 const: renesas,emev2-smu
[all …]
/linux/Documentation/devicetree/bindings/ptp/
H A Dfsl,ptp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QorIQ 1588 timer based PTP clock
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
19 - items:
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra30-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
18 clock from a group of clients. Typically, a system has a single Arbitration
20 Arbitration Domains to increase the effective system bandwidth.
22 Protocol Arbiter, which manage a related pool of memory devices. A system
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dbrcm,bcm2835-system-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/brcm,bcm2835-system-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM2835 System Timer
10 - Stefan Wahren <wahrenst@gmx.net>
11 - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
14 The System Timer peripheral provides four 32-bit timer channels and a
15 single 64-bit free running counter. Each channel has an output compare
21 const: brcm,bcm2835-system-timer
[all …]
H A Darm,armv7m-systick.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,armv7m-systick.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARMv7M System Timer
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
13 description: ARMv7-M includes a system timer, known as SysTick.
17 const: arm,armv7m-systick
25 clock-frequency: true
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Daudio-graph-port.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/audio-graph-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
15 port-base:
17 - $ref: /schemas/graph.yaml#/$defs/port-base
18 - $ref: /schemas/sound/dai-params.yaml#
20 mclk-fs:
21 $ref: simple-card.yaml#/definitions/mclk-fs
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Dst,nomadik-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,nomadik-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 STn8815. It was part of the prototype STn8500 which then became ST-Ericsson
15 - Linus Walleij <linus.walleij@linaro.org>
23 - st,nomadik-i2c
24 - mobileye,eyeq5-i2c
25 - mobileye,eyeq6h-i2c
27 - compatible
[all …]
H A Di2c-img-scb.txt4 - compatible: "img,scb-i2c"
5 - reg: Physical base address and length of controller registers
6 - interrupts: Interrupt number used by the controller
7 - clocks : Should contain a clock specifier for each entry in clock-names
8 - clock-names : Should contain the following entries:
9 "scb", for the SCB core clock.
10 "sys", for the system clock.
11 - clock-frequency: The I2C bus frequency in Hz
12 - #address-cells: Should be <1>
13 - #size-cells: Should be <0>
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dcirrus,lochnagar.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of
17 platform. Audio system topology, clocking and power can all be
25 [2] include/dt-bindings/pinctrl/lochnagar.h
26 [3] include/dt-bindings/clock/lochnagar.h
28 And these documents for the required sub-node binding details:
29 [4] Clock: ../clock/cirrus,lochnagar.yaml
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-devices-system-cpu1 What: /sys/devices/system/cpu/
2 Date: pre-git history
3 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
10 /sys/devices/system/cpu/cpuX/
12 What: /sys/devices/system/cpu/kernel_max
13 /sys/devices/system/cpu/offline
14 /sys/devices/system/cpu/online
15 /sys/devices/system/cpu/possible
16 /sys/devices/system/cpu/present
18 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
[all …]
/linux/Documentation/virt/kvm/x86/
H A Dtimekeeping.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
32 information relevant to KVM and hardware-based virtualization.
38 KVM clock are special enough to warrant a full exposition and are described in
41 2.1. i8254 - PIT
42 ----------------
45 or PIT. The PIT has a fixed frequency 1.193182 MHz base clock and three
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
59 -------------- ----------------
[all …]
/linux/Documentation/arch/x86/
H A Damd_hsmp.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Newer Fam19h(model 0x00-0x1f, 0x30-0x3f, 0x90-0x9f, 0xa0-0xaf),
8 Fam1Ah(model 0x00-0x1f) EPYC server line of processors from AMD support
9 system management functionality via HSMP (Host System Management Port).
11 The Host System Management Port (HSMP) is an interface to provide
12 OS-level software with access to system management functions via a
16 "7 Host System Management Port (HSMP)" of the family/model PPR
17 Eg: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/5589…
40 $ ls -al /dev/hsmp
41 crw-r--r-- 1 root root 10, 123 Jan 21 21:41 /dev/hsmp
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx27-phytec-phycore-rdk.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #include "imx27-phytec-phycore-som.dtsi"
9 compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";
12 stdout-path = &uart1;
16 model = "Sharp-LQ035Q7";
17 bits-per-pixel = <16>;
20 display-timings {
21 native-mode = <&timing0>;
23 clock-frequency = <5500000>;
26 hback-porch = <5>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210-smdkc110.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
10 * Board device tree source for YIC System SMDC110 board.
12 * NOTE: This file is completely based on original board file for mach-smdkc110
17 /dts-v1/;
18 #include <dt-bindings/input/input.h>
22 model = "YIC System SMDKC110 based on S5PC110";
34 pmic_ap_clk: clock-0 {
35 /* Workaround for missing PMIC and its clock */
36 compatible = "fixed-clock";
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dti,cc1352p7.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 - Ayush Singh <ayushdevel1325@gmail.com>
21 - description: high-frequency main system (MCU and peripherals) clock
22 - description: low-frequency system clock
24 clock-names:
26 - const: sclk_hf
27 - const: sclk_lf
29 reset-gpios:
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2836.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "bcm2835-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 local_intc: interrupt-controller@40000000 {
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a7-pmu";
[all …]
/linux/arch/powerpc/boot/
H A Dpq2.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include "fsl-soc.h"
17 #define PQ2_SCCR (0x10c80/4) /* System Clock Configuration Register */
18 #define PQ2_SCMR (0x10c88/4) /* System Clock Mode Register */
21 3, 2, 2, 2, 4, 4, 5, 9, 6, 11, 8, 10, 3, 12, 7, -1,
22 6, 5, 13, 2, 14, 4, 15, 9, 0, 11, 8, 10, 16, 12, 7, -1
25 /* Get various clocks from crystal frequency.
26 * Returns zero on failure and non-zero on success.
74 /* Set common device tree fields based on the given clock frequencies. */
83 setprop(node, "clock-frequency", &sysfreq, 4); in pq2_set_clocks()
[all …]
/linux/drivers/cpufreq/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "CPU Frequency scaling"
5 bool "CPU Frequency scaling"
7 CPU Frequency scaling allows you to change the clock speed of
9 the lower the CPU clock speed, the less power the CPU consumes.
12 clock speed, you need to either enable a dynamic cpufreq governor
16 <file:Documentation/admin-guide/pm/cpufreq.rst>.
31 bool "CPU frequency transition statistics"
33 Export CPU frequency statistics information through sysfs.
52 the frequency statically to the highest frequency supported by
[all …]
/linux/rust/kernel/
H A Dtime.rs1 // SPDX-License-Identifier: GPL-2.0
10 //! - The [`Instant`] type represents a specific point in time.
11 //! - The [`Delta`] type represents a span of time.
50 pub fn msecs_to_jiffies(msecs: Msecs) -> Jiffies { in msecs_to_jiffies()
56 /// Trait for clock sources.
58 /// Selection of the clock source depends on the use case. In some cases the usage of a
59 /// particular clock is mandatory, e.g. in network protocols, filesystems. In other
60 /// cases the user of the clock ha
[all...]
/linux/Documentation/admin-guide/pm/
H A Dcpufreq.rst1 .. SPDX-License-Identifier: GPL-2.0
19 different clock frequency and voltage configurations, often referred to as
20 Operating Performance Points or P-states (in ACPI terminology). As a rule,
21 the higher the clock frequency and the higher the voltage, the more instructions
22 can be retired by the CPU over a unit of time, but also the higher the clock
23 frequency and the higher the voltage, the more energy is consumed over a unit of
24 time (or the more power is drawn) by the CPU in the given P-state. Therefore
29 as possible and then there is no reason to use any P-states different from the
30 highest one (i.e. the highest-performance frequency/voltage configuration
37 different frequency/voltage configurations or (in the ACPI terminology) to be
[all …]

12345678910>>...32