Home
last modified time | relevance | path

Searched +full:sync +full:- +full:freq (Results 1 – 25 of 269) sorted by relevance

1234567891011

/linux/sound/drivers/vx/
H A Dvx_uer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * vx_modify_board_clock - tell the board that its clock has been modified
18 * @sync: DSP needs to resynchronize its FIFO
20 static int vx_modify_board_clock(struct vx_core *chip, int sync) in vx_modify_board_clock() argument
26 if (sync) in vx_modify_board_clock()
32 * vx_modify_board_inputs - resync audio inputs
44 * vx_read_one_cbit - read one bit from UER config
52 mutex_lock(&chip->lock); in vx_read_one_cbit()
53 if (chip->type >= VX_TYPE_VXPOCKET) { in vx_read_one_cbit()
62 mutex_unlock(&chip->lock); in vx_read_one_cbit()
[all …]
/linux/drivers/tty/serial/
H A Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
31 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) argument
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) argument
90 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
106 #define SYNC_ENAB 0 /* Sync Modes Enable */
111 #define MONSYNC 0 /* 8 Bit Sync character */
112 #define BISYNC 0x10 /* 16 bit sync character */
113 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
114 #define EXTSYNC 0x30 /* External Sync Mode */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
[all …]
H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) argument
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) argument
82 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
98 #define SYNC_ENAB 0 /* Sync Modes Enable */
103 #define MONSYNC 0 /* 8 Bit Sync character */
104 #define BISYNC 0x10 /* 16 bit sync character */
105 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
106 #define EXTSYNC 0x30 /* External Sync Mode */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
[all …]
H A Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
52 #define ZS_BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) argument
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) argument
109 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
124 #define SYNC_ENAB 0 /* Sync Modes Enable */
130 #define MONSYNC 0 /* 8 Bit Sync character */
131 #define BISYNC 0x10 /* 16 bit sync character */
132 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
133 #define EXTSYNC 0x30 /* External Sync Mode */
[all …]
H A Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
[all …]
/linux/sound/soc/fsl/
H A Dfsl_sai.c1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
26 #include "imx-pcm.h"
44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
57 /* current dir in async mode while opposite dir in sync mode */ in fsl_sai_dir_is_synced()
58 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
65 if (sai->is_pdm_mode) { in fsl_sai_get_pins_state()
68 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); in fsl_sai_get_pins_state()
72 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); in fsl_sai_get_pins_state()
[all …]
/linux/sound/soc/ti/
H A Ddavinci-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * based on davinci-mcasp.c DT support
30 #include "edma-pcm.h"
31 #include "davinci-i2s.h"
33 #define DRV_NAME "davinci-i2s"
38 * - This driver supports the "Audio Serial Port" (ASP),
41 * - But it labels it a "Multi-channel Buffered Serial Port"
43 * backward-compatible, possibly explaining that confusion.
45 * - OMAP chips have a controller called McBSP, which is
48 * - Newer DaVinci chips have a controller called McASP,
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dmaxim,max8952.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: regulator.yaml#
19 max8952,default-mode:
25 max8952,dvs-mode-microvolt:
35 max8952,en-gpio:
40 max8952,ramp-speed:
46 - 0: 32mV/us
[all …]
/linux/sound/soc/codecs/
H A Dmadera.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright (C) 2015-2019 Cirrus Logic, Inc. and
19 #include <linux/irqchip/irq-madera.h>
23 #include <sound/madera-pdata.h>
25 #include <dt-bindings/sound/madera.h>
144 dev_err(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
146 dev_warn(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
148 dev_dbg(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
151 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
153 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
[all …]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
90 /* Loop limit on how long we wait for auto-negotiation to complete */
172 /* 1000BASE-T Control Register */
176 /* 1000BASE-T Status Register */
239 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
263 #define IGC_ICR_TS BIT(19) /* Time Sync Interrupt */
282 #define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */
286 #define IGC_IMS_TS IGC_ICR_TS /* Time Sync Interrupt */
288 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
295 #define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
[all …]
/linux/sound/soc/stm/
H A Dstm32_sai_sub.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
10 #include <linux/clk-provider.h>
41 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
42 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
47 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
53 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
54 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm)
55 #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm)
56 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4((x)->pdata))
[all …]
/linux/include/linux/
H A Domap-gpmc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 #include <linux/platform_data/gpmc-omap.h>
15 * gpmc_nand_ops - Interface between NAND and GPMC
34 * gpmc_omap_onenand_set_timings - set optimized sync timings.
36 * @freq
55 gpmc_omap_onenand_set_timings(struct device * dev,int cs,int freq,int latency,struct gpmc_onenand_info * info) gpmc_omap_onenand_set_timings() argument
[all...]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 /** ice_dpll_pin - store info about pins
20 * @freq: current frequency of a pin
32 u32 freq; member
37 /** ice_dpll - store info required for DPLL control
48 * @dpll_state: current dpll sync state
49 * @prev_dpll_state: last dpll sync state
71 /** ice_dplls - store info required for CCU (clock controlling unit)
H A Dice_dpll.c1 // SPDX-License-Identifier: GPL-2.0
16 * enum ice_dpll_pin_type - enumerate ice pin types:
32 [ICE_DPLL_PIN_TYPE_RCLK_INPUT] = "rclk-input",
40 * ice_dpll_is_reset - check if reset is in progress
47 * * false - no reset in progress
48 * * true - reset in progress
52 if (ice_is_reset_in_progress(pf->state)) { in ice_dpll_is_reset()
60 * ice_dpll_pin_freq_set - set pin's frequency
64 * @freq: frequency to be set
69 * Context: Called under pf->dplls.lock
[all …]
/linux/tools/testing/selftests/net/forwarding/
H A Dtsn_lib.sh2 # SPDX-License-Identifier: GPL-2.0
3 # Copyright 2021-2022 NXP
13 # https://github.com/vladimiroltean/tsn-scripts
14 # WARNING: isochron versions pre-1.0 are unstable,
28 if ! [ -z "${uds_address}" ]; then
29 extra_args="${extra_args} -z ${uds_address}"
34 chrt -f 10 phc2sys -m \
35 -a -rr \
36 --step_threshold 0.00002 \
37 --first_step_threshold 0.00002 \
[all …]
/linux/drivers/dpll/
H A Ddpll_netlink.c1 // SPDX-License-Identifier: GPL-2.0
30 return (struct dpll_dump_ctx *)cb->ctx; in dpll_dump_context()
36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) in dpll_msg_add_dev_handle()
37 return -EMSGSIZE; in dpll_msg_add_dev_handle()
46 return -EMSGSIZE; in dpll_msg_add_dev_parent_handle()
52 * dpll_msg_add_pin_handle - attach pin handle attribute to a given message
57 * * 0 - success
58 * * -EMSGSIZE - no space in message to attach pin handle
64 if (nla_put_u32(msg, DPLL_A_PIN_ID, pin->id)) in dpll_msg_add_pin_handle()
65 return -EMSGSIZE; in dpll_msg_add_pin_handle()
[all …]
/linux/drivers/video/fbdev/i810/
H A Di810_gtf.c1 /*-*- linux-c -*-
2 * linux/drivers/video/i810_main.h -- Intel 810 Non-discrete Video Timings
20 * FIFO and Watermark tables - based almost wholly on i810_wmark.c in
26 u32 freq; member
116 * i810fb_encode_registers - encode @var to hardware register values
128 u8 __iomem *mmio = par->mmio_start_virtual; in i810fb_encode_registers()
133 n = ((xres + var->right_margin + var->hsync_len + in i810fb_encode_registers()
134 var->left_margin) >> 3) - 5; in i810fb_encode_registers()
135 par->regs.cr00 = (u8) n; in i810fb_encode_registers()
136 par->regs.cr35 = (u8) ((n >> 8) & 1); in i810fb_encode_registers()
[all …]
/linux/drivers/devfreq/
H A Dsun8i-a33-mbus.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // Copyright (C) 2020-2021 Samuel Holland <samuel@sholland.org>
25 #define MBUS_TMR_PERIOD(x) ((x) - 1)
28 #define MBUS_PMU_CFG_PERIOD(x) (((x) - 1) << 16)
108 return readl_relaxed(priv->reg_mbus + MBUS_TOTAL_BWCR); in sun8i_a33_mbus_get_peak_bw()
115 /* All PMU counters are cleared on a disable->enable transition. */ in sun8i_a33_mbus_restart_pmu_counters()
117 priv->reg_mbus + MBUS_PMU_CFG); in sun8i_a33_mbus_restart_pmu_counters()
119 priv->reg_mbus + MBUS_PMU_CFG); in sun8i_a33_mbus_restart_pmu_counters()
130 * ------------- * ------------ * -------- in sun8i_a33_mbus_update_nominal_bw()
133 priv->nominal_bw = ddr_freq_mhz * pmu_period * priv->data_width / 1024; in sun8i_a33_mbus_update_nominal_bw()
[all …]
/linux/drivers/video/fbdev/geode/
H A Dlxfb_ops.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
23 /* This is the complete list of PLL frequencies that we can set -
25 * freq is the frequency of the dotclock * 1000 (for example,
32 unsigned int freq; member
163 unsigned int freq, i; in lx_set_clock() local
165 freq = (unsigned int) (1000000000 / info->var.pixclock); in lx_set_clock()
167 min = abs(pll_table[0].freq - freq); in lx_set_clock()
170 diff = abs(pll_table[i].freq - freq); in lx_set_clock()
182 struct lxfb_par *par = info->par; in lx_graphics_disable()
[all …]
/linux/drivers/scsi/
H A Dmac53c94.h1 /* SPDX-License-Identifier: GPL-2.0 */
142 * Encoding for sync transfer period.
155 * Encoding for sync offset.
175 #define CLKF_VAL(freq) ((((freq) + 4999999) / 5000000) & CLKF_MASK) argument
182 #define TEST_TRISTATE 4 /* tristate (hi-z) test mode */
/linux/drivers/iio/imu/
H A Dadis16475.c1 // SPDX-License-Identifier: GPL-2.0
113 const struct adis16475_sync *sync; member
171 struct adis16475 *st = file->private_data; in adis16475_show_firmware_revision()
177 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_REV, &rev); in adis16475_show_firmware_revision()
197 struct adis16475 *st = file->private_data; in adis16475_show_firmware_date()
203 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_Y, &year); in adis16475_show_firmware_date()
207 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_DM, &md); in adis16475_show_firmware_date()
211 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", md >> 8, md & 0xff, in adis16475_show_firmware_date()
230 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_SERIAL_NUM, &serial); in adis16475_show_serial_number()
247 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_PROD_ID, &prod_id); in adis16475_show_product_id()
[all …]
/linux/drivers/staging/media/av7110/
H A Dav7110_v4l.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * - video4linux interface for DVB and Siemens DVB-C analog module
6 * Copyright (C) 1999-2002 Ralph Metzler
10 * Copyright (C) 1998,1999 Christian Theiss <mistert@rz.fh-augsburg.de>
33 switch (av7110->adac_type) { in msp_writereg()
44 if (i2c_transfer(&av7110->i2c_adap, &msgs, 1) != 1) { in msp_writereg()
45 dprintk(1, "failed @ card %d, %u = %u\n", av7110->dvb_adapter.num, reg, val); in msp_writereg()
46 return -EIO; in msp_writereg()
60 switch (av7110->adac_type) { in msp_readreg()
73 if (i2c_transfer(&av7110->i2c_adap, &msgs[0], 2) != 2) { in msp_readreg()
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_mdss.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
297 * struct dpu_hw_fmt_layout - format information of the source pixel data
326 * struct dpu_mdss_color - mdss color description
358 * struct dpu_hw_tear_check - Struct contains parameters to configure
359 * tear-effect module. This structure is used to configure tear-check
360 * logic present either in ping-pong or in interface module.
361 * @vsync_count: Ratio of MDP VSYNC clk freq(Hz) to refresh rate divided
363 * @sync_cfg_height: Total vertical lines (display height - 1)
371 * @hw_vsync_mode: Sync with external frame sync input
[all …]
/linux/drivers/scsi/aic7xxx/
H A Daic7xxx_proc.c2 * Copyright (c) 2000-2001 Adaptec Inc.
16 * 3. Neither the names of the above-listed copyright holders nor the names
37 * String handling code courtesy of Gerard Roudier's <groudier@club-internet.fr>
61 { 0x08, 625 }, /* FAST-160 */
62 { 0x09, 1250 }, /* FAST-80 */
63 { 0x0a, 2500 }, /* FAST-40 40MHz */
64 { 0x0b, 3030 }, /* FAST-40 33MHz */
65 { 0x0c, 5000 } /* FAST-20 */
70 * sync period factor.
97 u_int freq; in ahc_format_transinfo() local
[all …]
H A Daic79xx_proc.c2 * Copyright (c) 2000-2001 Adaptec Inc.
16 * 3. Neither the names of the above-listed copyright holders nor the names
37 * String handling code courtesy of Gerard Roudier's <groudier@club-internet.fr>
60 { 0x08, 625 }, /* FAST-160 */
61 { 0x09, 1250 }, /* FAST-80 */
62 { 0x0a, 2500 }, /* FAST-40 40MHz */
63 { 0x0b, 3030 }, /* FAST-40 33MHz */
64 { 0x0c, 5000 } /* FAST-20 */
69 * sync period factor.
96 u_int freq; in ahd_format_transinfo() local
[all …]

1234567891011