Lines Matching +full:sync +full:- +full:freq
1 /* SPDX-License-Identifier: GPL-2.0 */
90 /* Loop limit on how long we wait for auto-negotiation to complete */
172 /* 1000BASE-T Control Register */
176 /* 1000BASE-T Status Register */
239 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
263 #define IGC_ICR_TS BIT(19) /* Time Sync Interrupt */
282 #define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */
286 #define IGC_IMS_TS IGC_ICR_TS /* Time Sync Interrupt */
288 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
295 #define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
334 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
406 #define IGC_DTXMXPKTSZ_DEFAULT 0x98 /* 9728-byte Jumbo frames */
423 /* Time Sync Interrupt Causes */
438 /* Time Sync Receive Control bit definitions */
449 /* Time Sync Receive Configuration */
464 /* Time Sync Transmit Control bit definitions */
471 #define IGC_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */
472 #define IGC_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */
473 #define IGC_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */
521 #define IGC_TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */
522 #define IGC_TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */
526 #define IGC_TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */
527 #define IGC_TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */
531 #define IGC_TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */
532 #define IGC_TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */
536 #define IGC_TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */
537 #define IGC_TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */
595 #define IGC_PTM_STAT_ADJUST_CYC BIT(5) /* 1588 timer adjusted during non-1st PTM cycle */
601 /* GPY211 - I225 defines */
614 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
615 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
619 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
640 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
641 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
659 /* EEE Link-Partner Ability */
664 #define IGC_N0_QUEUE -1
695 /* Minimum time for 100BASE-T where no data will be transmit following move out