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/linux/Documentation/networking/devlink/
H A Ddevlink-eswitch-attr.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Devlink E-Switch Attribute
7 Devlink E-Switch supports two modes of operation: legacy and switchdev.
8 Legacy mode operates based on traditional MAC/VLAN steering rules. Switching
12 On the other hand, switchdev mode allows for more advanced offloading
13 capabilities of the E-Switch to hardware. In switchdev mode, more switching
14 rules and logic can be offloaded to the hardware switch ASIC. It enables
16 or scalable-functions (SFs) of the device. See more information about
20 In addition, the devlink E-Switch also comes with other attributes listed
26 The following is a list of E-Switch attributes.
[all …]
/linux/drivers/soc/fsl/qe/
H A Ducc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * QE UCC API Set - UCC specific routines implementations.
33 if (ucc_num > UCC_MAX_NUM - 1) in ucc_set_qe_mux_mii_mng()
34 return -EINVAL; in ucc_set_qe_mux_mii_mng()
37 qe_clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG, in ucc_set_qe_mux_mii_mng()
50 * 'ucc_num' is the UCC number, from 0 - 7.
61 switch (ucc_num) { in ucc_set_type()
62 case 0: guemr = &qe_immr->ucc1.slow.guemr; in ucc_set_type()
64 case 1: guemr = &qe_immr->ucc2.slow.guemr; in ucc_set_type()
66 case 2: guemr = &qe_immr->ucc3.slow.guemr; in ucc_set_type()
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dqcom,rpm-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/qcom,rpm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 The regulator node houses sub-nodes for each regulator within the device.
16 Each sub-node is identified using the node's name, with valid values listed
28 l29, lvs1, lvs2, lvs3, lvs4, lvs5, lvs6, lvs7, usb-switch, hdmi-switch,
37 - Bjorn Andersson <andersson@kernel.org>
42 - qcom,rpm-pm8058-regulators
43 - qcom,rpm-pm8901-regulators
[all …]
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmscc,ocelot.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Ocelot Switch Family
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
20 them performs packet I/O primarily through an Ethernet port of the switch
[all …]
H A Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
[all …]
H A Dmarvell,mv88e6xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MV88E6xxx DSA switch family
10 - Andrew Lunn <andrew@lunn.ch>
13 The Marvell MV88E6xxx switch series has been produced and sold
14 by Marvell since at least 2008. The switch has a few compatibles which
15 just indicate the base address of the switch, then operating systems
16 can investigate switch ID registers to find out which actual version
17 of the switch it is dealing with.
[all …]
H A Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros QCA83xx switch family
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17 the switch node and declare the phandle for the port, referencing the internal
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
20 mdio-bus configurations are not supported by the hardware.
[all …]
H A Dqca,ar9331.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR9331 built-in switch
10 - Oleksij Rempel <o.rempel@pengutronix.de>
13 Qualcomm Atheros AR9331 is a switch built-in to Atheros AR9331 WiSoC and
14 addressable over internal MDIO bus. All PHYs are built-in as well.
18 const: qca,ar9331-switch
26 interrupt-controller: true
28 '#interrupt-cells':
[all …]
H A Dlan9303.txt1 SMSC/MicroChip LAN9303 three port ethernet switch
2 -------------------------------------------------
6 - compatible: should be
7 - "smsc,lan9303-i2c" for I2C managed mode
9 - "smsc,lan9303-mdio" for mdio managed mode
13 - reset-gpios: GPIO to be used to reset the whole device
14 - reset-duration: reset duration in milliseconds, defaults to 200 ms
18 The integrated switch subnode should be specified according to the binding
19 described in dsa/dsa.txt. The CPU port of this switch is always port 0.
23 auto-detected and mapped accordingly.
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-driver-bd9571mwv-regulator1 What: /sys/bus/i2c/devices/.../bd9571mwv-regulator.*.auto/backup_mode
5 Description: Read/write the current state of DDR Backup Mode, which controls
10 A. With a momentary power switch (or pulse signal), DDR
11 Backup Mode is enabled by default when available, as the
13 B. With a toggle power switch (or level signal), the
16 1. Configure PMIC for backup mode, to change the role of
17 the accessory power switch from a power switch to a
18 wake-up switch,
19 2. Switch accessory power switch off, to prepare for
23 4. Switch accessory power switch on, to resume the
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
27 - mediatek,mt8186-mtu3
[all …]
H A Ddwc2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: usb-drd.yaml#
14 - $ref: usb-hcd.yaml#
19 - const: brcm,bcm2835-usb
20 - const: hisilicon,hi6220-usb
21 - const: ingenic,jz4775-otg
22 - const: ingenic,jz4780-otg
[all …]
H A Dqcom,wcd939x-usbss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,wcd939x-usbss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm WCD9380/WCD9385 USB SubSystem Altmode/Analog Audio Switch
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 Qualcomm WCD9390/WCD9395 is a standalone Hi-Fi audio codec IC with a
14 functionally separate USB SubSystem for Altmode/Analog Audio Switch
17 USB-C Mux subsystems are external to the IC, thus requiring DT port-endpoint
18 graph description to handle USB-C altmode & orientation switching for Audio
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
[all …]
H A Dmicrochip,lan966x-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Lan966x Ethernet switch controller
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
[all …]
H A Dhisilicon-hns-nic.txt4 - compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2".
5 "hisilicon,hns-nic-v1" is for hip05.
6 "hisilicon,hns-nic-v2" is for Hi1610 and Hi1612.
7 - ae-handle: accelerator engine handle for hns,
9 see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
10 - port-id: is the index of port provided by DSAF (the accelerator). DSAF can
14 The remaining 6 PHYs are taken according to the mode of DSAF.
16 In NIC mode of DSAF, all 6 PHYs are taken as ethernet ports to the CPU. The
17 port-id can be 2 to 7. Here is the diagram:
18 +-----+---------------+
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Datombios_crtc.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
31 #include "atom-bits.h"
39 struct drm_display_mode *mode, in amdgpu_atombios_crtc_overscan_setup() argument
42 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_overscan_setup()
51 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_overscan_setup()
53 switch (amdgpu_crtc->rmx_type) { in amdgpu_atombios_crtc_overscan_setup()
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
[all …]
/linux/sound/soc/codecs/
H A Dmax9867.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright 2013-2015 Maxim Integrated Products
6 // Copyright 2018 Ladislav Michl <ladis@linux-mips.org>
42 "Butterworth/8-24"
55 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max9867_adc_dac_event()
71 max9867->adc_dac_active |= BIT(adc_dac); in max9867_adc_dac_event()
73 max9867->adc_dac_active &= ~BIT(adc_dac); in max9867_adc_dac_event()
86 ret = regmap_read(max9867->regmap, MAX9867_CODECFLTR, &reg); in max9867_filter_get()
88 return -EINVAL; in max9867_filter_get()
91 ucontrol->value.enumerated.item[0] = 1; in max9867_filter_get()
[all …]
H A Dtwl4030.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/mfd/twl4030-audio.h>
64 u8 ctl_cache[TWL4030_REG_PRECKR_CTL - TWL4030_REG_EAR_CTL + 1];
76 twl4030->ctl_cache[i - TWL4030_REG_EAR_CTL] = byte; in tw4030_init_ctl_cache()
86 return -EIO; in twl4030_read()
88 switch (reg) { in twl4030_read()
95 value = twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL]; in twl4030_read()
111 switch (reg) { in twl4030_can_write_to_chip()
113 if (twl4030->earpiece_enabled) in twl4030_can_write_to_chip()
117 if (twl4030->predrivel_enabled) in twl4030_can_write_to_chip()
[all …]
/linux/tools/testing/selftests/drivers/net/bonding/
H A Dlag_lib.sh2 # SPDX-License-Identifier: GPL-2.0
11 local mode=$2
21 ip link add "$name" up type bond mode "$mode"
26 teamd -d -c '
30 "name": "'"$mode"'"
47 # Used to test dev->uc handling
49 # Used to test dev->mc handling
60 check_err $? "IPv6 solicited-node multicast mac address not found on a slave"
69 check_err $? "IPv6 solicited-node multicast mac address still present on a slave"
73 log_test "$driver cleanup mode $mode"
[all …]
/linux/drivers/mfd/
H A Ducb1x00-ts.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Touchscreen driver for UCB1x00-based touchscreens
8 * 21-Jan-2002 <jco@ict.es> :
10 * Added support for synchronous A/D mode. This mode is useful to
34 #include <asm/mach-types.h>
56 struct input_dev *idev = ts->idev; in ucb1x00_ts_evt_add()
67 struct input_dev *idev = ts->idev; in ucb1x00_ts_event_release()
75 * Switch to interrupt mode.
79 ucb1x00_reg_write(ts->ucb, UCB_TS_CR, in ucb1x00_ts_mode_int()
86 * Switch to pressure mode, and read pressure. We don't need to wait
[all …]
/linux/Documentation/sound/cards/
H A Dcmipci.rst2 Brief Notes on C-Media 8338/8738/8768/8770 Driver
8 Front/Rear Multi-channel Playback
9 ---------------------------------
13 DACs, both streams are handled independently unlike the 4/6ch multi-
22 - The first DAC supports U8 and S16LE formats, while the second DAC
24 - The second DAC supports only two channel stereo.
30 The rear output can be heard only when "Four Channel Mode" switch is
35 When "Four Channel Mode" switch is off, the output from rear speakers
38 before your turn off this switch.
44 on and "double DAC" mode. Actually I could hear separate 4 channels
[all …]
/linux/arch/arm/mach-tegra/
H A Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
29 #include <asm/proc-fns.h>
50 switch (tegra_get_chip_id()) { in tegra_tear_down_cpu_init()
141 if (tegra_cpu_car_ops->rail_off_ready && in tegra_sleep_cpu()
143 return -EBUSY; in tegra_sleep_cpu()
148 * MMU-on if cache maintenance is done via Trusted Foundations in tegra_sleep_cpu()
150 * if any of secondary CPU's is online and this is the LP2-idle in tegra_sleep_cpu()
151 * code-path only for Tegra20/30. in tegra_sleep_cpu()
162 * 2) Disable D-cache. This need to be taken into account in in tegra_sleep_cpu()
[all …]
/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp_target.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
26 * 32-bit or 64-bit words. All others are not listed.
35 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { in target_rw()
40 return -EINVAL; in target_rw()
46 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { in nfp6000_nbi_dma()
51 return -EINVAL; in nfp6000_nbi_dma()
57 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { in nfp6000_nbi_stats()
62 return -EINVAL; in nfp6000_nbi_stats()
68 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { in nfp6000_nbi_tm()
[all …]
/linux/drivers/net/ethernet/ti/
H A Dcpsw-phy-sel.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Texas Instruments Ethernet Switch Driver
44 u32 mode = 0; in cpsw_gmii_sel_am3352() local
47 reg = readl(priv->gmii_sel); in cpsw_gmii_sel_am3352()
49 switch (phy_mode) { in cpsw_gmii_sel_am3352()
51 mode = AM33XX_GMII_SEL_MODE_RMII; in cpsw_gmii_sel_am3352()
55 mode = AM33XX_GMII_SEL_MODE_RGMII; in cpsw_gmii_sel_am3352()
61 mode = AM33XX_GMII_SEL_MODE_RGMII; in cpsw_gmii_sel_am3352()
66 dev_warn(priv->dev, in cpsw_gmii_sel_am3352()
67 "Unsupported PHY mode: \"%s\". Defaulting to MII.\n", in cpsw_gmii_sel_am3352()
[all …]

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