1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
29 #include <asm/proc-fns.h>
50 	switch (tegra_get_chip_id()) {  in tegra_tear_down_cpu_init()
141 	if (tegra_cpu_car_ops->rail_off_ready &&  in tegra_sleep_cpu()
143 		return -EBUSY;  in tegra_sleep_cpu()
148 	 * MMU-on if cache maintenance is done via Trusted Foundations  in tegra_sleep_cpu()
150 	 * if any of secondary CPU's is online and this is the LP2-idle  in tegra_sleep_cpu()
151 	 * code-path only for Tegra20/30.  in tegra_sleep_cpu()
162 	 *  2) Disable D-cache. This need to be taken into account in  in tegra_sleep_cpu()
164 	 *     shall avoid the re-disable.  in tegra_sleep_cpu()
177 static void tegra_pm_set(enum tegra_suspend_mode mode)  in tegra_pm_set()  argument
181 	switch (tegra_get_chip_id()) {  in tegra_pm_set()
194 	tegra_pmc_enter_suspend_mode(mode);  in tegra_pm_set()
206 	err = cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);  in tegra_pm_enter_lp2()
209 	 * Resume L2 cache if it wasn't re-enabled early during resume,  in tegra_pm_enter_lp2()
210 	 * which is the case for Tegra30 that has to re-enable the cache  in tegra_pm_enter_lp2()
212 	 * hence re-enabling is a no-op. This is always a no-op on Tegra114+.  in tegra_pm_enter_lp2()
225 				enum tegra_suspend_mode mode)  in tegra_pm_validate_suspend_mode()  argument
230 	if (mode > TEGRA_SUSPEND_LP1)  in tegra_pm_validate_suspend_mode()
233 	return mode;  in tegra_pm_validate_suspend_mode()
239 	 * Cache have to be disabled with MMU-on if cache maintenance is done  in tegra_sleep_core()
240 	 * via Trusted Foundations firmware. This is a no-op on Tegra114+.  in tegra_sleep_core()
259  * Hooking the address of LP1 reset vector and SDRAM self-refresh code in
266 	switch (tegra_get_chip_id()) {  in tegra_lp1_iram_hook()
286 	iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr;  in tegra_lp1_iram_hook()
296 	switch (tegra_get_chip_id()) {  in tegra_sleep_core_init()
348 	enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();  in tegra_suspend_enter()  local
350 	if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||  in tegra_suspend_enter()
351 		    mode >= TEGRA_MAX_SUSPEND_MODE))  in tegra_suspend_enter()
352 		return -EINVAL;  in tegra_suspend_enter()
354 	pr_info("Entering suspend state %s\n", lp_state[mode]);  in tegra_suspend_enter()
356 	tegra_pm_set(mode);  in tegra_suspend_enter()
361 	switch (mode) {  in tegra_suspend_enter()
372 	cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);  in tegra_suspend_enter()
375 	 * Resume L2 cache if it wasn't re-enabled early during resume,  in tegra_suspend_enter()
376 	 * which is the case for Tegra30 that has to re-enable the cache  in tegra_suspend_enter()
378 	 * hence re-enabling is a no-op.  in tegra_suspend_enter()
382 	switch (mode) {  in tegra_suspend_enter()
408 	enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();  in tegra_pm_init_suspend()  local
410 	if (mode == TEGRA_SUSPEND_NONE)  in tegra_pm_init_suspend()
415 	if (mode >= TEGRA_SUSPEND_LP1) {  in tegra_pm_init_suspend()
418 			       "self-refresh -- LP0/LP1 unavailable\n",  in tegra_pm_init_suspend()
421 			mode = TEGRA_SUSPEND_LP2;  in tegra_pm_init_suspend()
426 	switch (mode) {  in tegra_pm_init_suspend()
451 	return -EINVAL;  in tegra_pm_park_secondary_cpu()