Home
last modified time | relevance | path

Searched +full:sw +full:- +full:reset +full:- +full:number (Results 1 – 25 of 424) sorted by relevance

12345678910>>...17

/linux/Documentation/devicetree/bindings/reset/
H A Dnuvoton,npcm750-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton NPCM Reset controller
10 - Tomer Maimon <tmaimon77@gmail.com>
15 - nuvoton,npcm750-reset # Poleg NPCM7XX SoC
16 - nuvoton,npcm845-reset # Arbel NPCM8XX SoC
21 '#reset-cells':
24 '#clock-cells':
[all …]
/linux/drivers/thunderbolt/
H A Dlc.c1 // SPDX-License-Identifier: GPL-2.0
14 * tb_lc_read_uuid() - Read switch UUID from link controller common register
15 * @sw: Switch whose UUID is read
18 int tb_lc_read_uuid(struct tb_switch *sw, u32 *uuid) in tb_lc_read_uuid() argument
20 if (!sw->cap_lc) in tb_lc_read_uuid()
21 return -EINVAL; in tb_lc_read_uuid()
22 return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4); in tb_lc_read_uuid()
25 static int read_lc_desc(struct tb_switch *sw, u32 *desc) in read_lc_desc() argument
27 if (!sw->cap_lc) in read_lc_desc()
28 return -EINVAL; in read_lc_desc()
[all …]
H A Ddma_port.c1 // SPDX-License-Identifier: GPL-2.0
48 * struct tb_dma_port - DMA control port
49 * @sw: Switch the DMA port belongs to
50 * @port: Switch port number where DMA capability is found
55 struct tb_switch *sw; member
68 u64 route = tb_cfg_get_route(pkg->buffer) & ~BIT_ULL(63); in dma_port_match()
70 if (pkg->frame.eof == TB_CFG_PKG_ERROR) in dma_port_match()
72 if (pkg->frame.eof != req->response_type) in dma_port_match()
74 if (route != tb_cfg_get_route(req->request)) in dma_port_match()
76 if (pkg->frame.size != req->response_size) in dma_port_match()
[all …]
H A Dswitch.c1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt driver - switch/port utility functions
12 #include <linux/nvmem-provider.h>
37 static struct nvm_auth_status *__nvm_get_auth_status(const struct tb_switch *sw) in __nvm_get_auth_status() argument
42 if (uuid_equal(&st->uuid, sw->uuid)) in __nvm_get_auth_status()
49 static void nvm_get_auth_status(const struct tb_switch *sw, u32 *status) in nvm_get_auth_status() argument
54 st = __nvm_get_auth_status(sw); in nvm_get_auth_status()
57 *status = st ? st->status : 0; in nvm_get_auth_status()
60 static void nvm_set_auth_status(const struct tb_switch *sw, u32 status) in nvm_set_auth_status() argument
64 if (WARN_ON(!sw->uuid)) in nvm_set_auth_status()
[all …]
/linux/include/linux/soc/ti/
H A Dk3-ringacc.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
16 * enum k3_ring_mode - &struct k3_ring_cfg mode
20 * @K3_RINGACC_RING_MODE_RING: Exposed Ring mode for SW direct access
24 * controls the entire state of the queue, and SW has no directly control,
26 * This is particularly useful when more than one SW or HW entity can be
41 * enum k3_ring_size - &struct k3_ring_cfg elm_size
60 * enum k3_ring_cfg - RA ring configuration structure
62 * @size: Ring size, number of elements
86 #define K3_RINGACC_RING_ID_ANY (-1)
[all …]
/linux/include/linux/mfd/
H A Daltera-a10sr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
27 * the number of GPIO in each register. We then need to multiply
39 #define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */
41 #define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid */
45 #define ALTR_A10SR_PBDSW_REG 0x04 /* PB & DIP SW - Input only */
46 #define ALTR_A10SR_PBDSW_IRQ_REG 0x06 /* PB & DIP SW Flag Clear */
55 #define ALTR_A10SR_HPS_RST_REG 0x10 /* HPS Reset */
56 #define ALTR_A10SR_USB_QSPI_REG 0x12 /* USB, BQSPI, FILE Reset */
60 #define ALTR_A10SR_WARM_RST_REG 0x1A /* HPS Warm Reset */
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dadi,ad7606.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
14 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7605-4.pdf
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606_7606-6_7606-4.pdf
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7606B.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606c-16.pdf
18 https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606c-18.pdf
19 https://www.analog.com/media/en/technical-documentation/data-sheets/ad7607.pdf
[all …]
/linux/drivers/net/ethernet/sun/
H A Dsunhme.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GREG_SWRESET 0x000UL /* Software Reset */
21 /* Global reset register. */
38 #define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
39 #define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
40 #define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
42 #define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
46 #define GREG_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
47 #define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
48 #define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
[all …]
/linux/arch/alpha/kernel/
H A Dsignal.c1 // SPDX-License-Identifier: GPL-2.0
7 * 1997-11-02 Modified for POSIX.1b signals by Richard Henderson
69 __get_user(new_ka.sa.sa_handler, &act->sa_handler) || in SYSCALL_DEFINE3()
70 __get_user(new_ka.sa.sa_flags, &act->sa_flags) || in SYSCALL_DEFINE3()
71 __get_user(mask, &act->sa_mask)) in SYSCALL_DEFINE3()
72 return -EFAULT; in SYSCALL_DEFINE3()
81 __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || in SYSCALL_DEFINE3()
82 __put_user(old_ka.sa.sa_flags, &oact->sa_flags) || in SYSCALL_DEFINE3()
83 __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask)) in SYSCALL_DEFINE3()
84 return -EFAULT; in SYSCALL_DEFINE3()
[all …]
/linux/Documentation/devicetree/bindings/thermal/
H A Dnvidia,tegra124-soctherm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/nvidia,tegra124-soctherm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 polled or interrupt-based thermal monitoring, CPU and GPU throttling based
21 - nvidia,tegra124-soctherm
22 - nvidia,tegra132-soctherm
23 - nvidia,tegra210-soctherm
[all …]
/linux/arch/openrisc/kernel/
H A Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
26 #include <asm/asm-offsets.h>
30 l.movhi rd,hi(-KERNELBASE) ;\
73 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
76 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
79 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
82 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
85 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
88 #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
[all …]
/linux/drivers/net/ethernet/intel/e1000e/
H A Ddefines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
36 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
46 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
100 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
182 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
183 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
185 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_common.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2023, Intel Corporation. */
90 * ice_dump_phy_type - helper function to dump phy_type
117 * ice_set_mac_type - Sets MAC type
125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) in ice_set_mac_type()
126 return -ENODEV; in ice_set_mac_type()
128 switch (hw->device_id) { in ice_set_mac_type()
135 hw->mac_type = ICE_MAC_E810; in ice_set_mac_type()
156 hw->mac_type = ICE_MAC_GENERIC; in ice_set_mac_type()
162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; in ice_set_mac_type()
[all …]
H A Dice_sched.c1 // SPDX-License-Identifier: GPL-2.0
8 * ice_sched_add_root_node - Insert the Tx scheduler root node in SW DB
13 * to the SW DB.
23 return -EINVAL; in ice_sched_add_root_node()
25 hw = pi->hw; in ice_sched_add_root_node()
29 return -ENOMEM; in ice_sched_add_root_node()
31 root->children = devm_kcalloc(ice_hw_to_dev(hw), hw->max_children[0], in ice_sched_add_root_node()
32 sizeof(*root->children), GFP_KERNEL); in ice_sched_add_root_node()
33 if (!root->children) { in ice_sched_add_root_node()
35 return -ENOMEM; in ice_sched_add_root_node()
[all …]
/linux/drivers/net/ethernet/tehuti/
H A Dtehuti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * RX HW/SW interaction overview
12 * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
13 * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
16 * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
17 * filled by HW and is readen by SW. Each descriptor holds status and ID.
23 * One holds 1.5K packets and another - 26K packets. Depending on incoming
28 * RX SW Data Structures
30 * skb db - used to keep track of all skbs owned by SW and their dma addresses.
34 * fifo - keeps info about fifo's size and location, relevant HW registers,
[all …]
/linux/drivers/usb/host/
H A Dxhci-caps.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 /* bits 7:0 - how long is the Capabilities register */
9 /* HCSPARAMS1 - hcs_params1 - bitmasks */
15 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
18 /* HCSPARAMS2 - hcs_params2 - bitmasks */
19 /* bits 0:3, frames or uframes that SW need
[all...]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/
H A Ddcn20_stream_encoder.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
36 enc1->base.ctx->logger
39 (enc1->regs->reg)
43 enc1->se_shift->field_name, enc1->se_mask->field_name
47 enc1->base.ctx
57 if (info_packet->valid) { in enc2_update_hdmi_info_packet()
63 /* enable transmission of packet(s) - in enc2_update_hdmi_info_packet()
68 /* select line number to send packets on */ in enc2_update_hdmi_info_packet()
76 /* DP_SEC_GSP[x]_LINE_REFERENCE - keep default value REFER_TO_DP_SOF */ in enc2_update_hdmi_info_packet()
155 enc2_update_hdmi_info_packet(enc1, 0, &info_frame->avi); in enc2_stream_encoder_update_hdmi_info_packets()
[all …]
/linux/drivers/net/ethernet/intel/idpf/
H A Didpf_txrx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
27 /* Number of descriptors in a queue should be a multiple of 32. RX queue
69 * many descriptors. This macro divides a given number of RX descriptors by
70 * number of buffer queues to calculate how many descriptors each buffer queue
75 * descriptors before SW gets an interrupt and overwrites SW head, the gen bit
77 * be gone forever and SW has no reasonable way to tell that this has happened.
78 * From SW perspective, when we finally get an interrupt, it looks like we're
83 #define IDPF_RX_BUFQ_WORKING_SET(rxq) ((rxq)->desc_count - 1)
87 if (unlikely(++(ntc) == (rxq)->desc_count)) { \
95 if (unlikely(++(idx) == (q)->desc_count)) \
[all …]
/linux/drivers/net/ethernet/micrel/
H A Dksz884x.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/net/ethernet/micrel/ksx884x.c - Micrel KSZ8841/2 PCI Ethernet driver
5 * Copyright (c) 2009-2010 Micrel, Inc.
271 #define PHY_CTRL_INTERVAL (KS884X_P2MBCR_P - KS884X_P1MBCR_P)
293 #define PHY_SPECIAL_INTERVAL (KS884X_P2VCT_P - KS884X_P1VCT_P)
482 (KS8842_PORT_2_CTRL_1 - KS8842_PORT_1_CTRL_1))
587 #define STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
588 #define STATIC_MAC_TABLE_FWD_PORTS 00-00070000-00000000
589 #define STATIC_MAC_TABLE_VALID 00-00080000-00000000
590 #define STATIC_MAC_TABLE_OVERRIDE 00-00100000-00000000
[all …]
/linux/drivers/clk/qcom/
H A Dgdsc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
17 * struct gdsc - Globally Distributed Switch Controller
21 * @collapse_ctrl: APCS collapse-vote register
22 * @collapse_mask: APCS collapse-vote mask
25 * @cxc_count: number of @cxcs
31 * @reset_count: number of @resets
32 * @rcdev: reset controller
52 * There is no SW control to transition a GDSC into
95 return -ENOSYS; in gdsc_register()
/linux/Documentation/devicetree/bindings/net/
H A Dsnps,dwc-qos-ethernet.txt7 IP block. The IP supports multiple options for bus type, clocking and reset
8 structure, and feature list. Consequently, a number of properties and list
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A De1000_i210.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
17 * igb_get_hw_semaphore_i210 - Acquire hardware semaphore
25 s32 timeout = hw->nvm.word_size + 1; in igb_get_hw_semaphore_i210()
28 /* Get the SW semaphore */ in igb_get_hw_semaphore_i210()
39 /* In rare circumstances, the SW semaphore may already be held in igb_get_hw_semaphore_i210()
42 if (hw->dev_spec._82575.clear_semaphore_once) { in igb_get_hw_semaphore_i210()
43 hw->dev_spec._82575.clear_semaphore_once = false; in igb_get_hw_semaphore_i210()
56 hw_dbg("Driver can't access device - SMBI bit is set.\n"); in igb_get_hw_semaphore_i210()
57 return -E1000_ERR_NVM; in igb_get_hw_semaphore_i210()
[all …]
/linux/Documentation/networking/
H A Dpktgen.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Enable CONFIG_NET_PKTGEN to compile and build pktgen either in-kernel
16 root 129 0.3 0.0 0 0 ? SW 2003 523:20 [kpktgend_0]
17 root 130 0.3 0.0 0 0 ? SW 2003 509:50 [kpktgend_1]
31 overload type of benchmarking, as this could hurt the normal use-case.
35 # ethtool -G ethX tx 1024
44 ring-buffers for various performance reasons, and packets stalling
49 and the cleanup interval is affected by the ethtool --coalesce setting
50 of parameter "rx-usecs".
54 # ethtool -C ethX rx-usecs 30
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_i2c_hw.c32 dce_i2c_hw->ctx
34 dce_i2c_hw->regs->reg
38 dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name
56 DC_I2C_TRANSACTION_COUNT, dce_i2c_hw->transaction_count - 1); in execute_transaction()
64 dce_i2c_hw->transaction_count = 0; in execute_transaction()
65 dce_i2c_hw->buffer_used_bytes = 0; in execute_transaction()
77 else if (value & dce_i2c_hw->masks->DC_I2C_SW_STOPPED_ON_NACK) in get_channel_status()
79 else if (value & dce_i2c_hw->masks->DC_I2C_SW_TIMEOUT) in get_channel_status()
81 else if (value & dce_i2c_hw->masks->DC_I2C_SW_ABORTED) in get_channel_status()
83 else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE) in get_channel_status()
[all …]

12345678910>>...17