Lines Matching +full:sw +full:- +full:reset +full:- +full:number
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
36 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
46 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
100 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
182 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
183 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
185 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
192 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
193 #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */
200 #define E1000_CTRL_RST 0x04000000 /* Global reset */
204 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
222 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
238 /* 1000/H is not supported, nor spec-compliant. */
292 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
374 /* SW Semaphore Register */
476 * Number of high/low register pairs in the RAR. The RAR (Receive Address
504 /* Loop limit on how long we wait for auto-negotiation to complete */
509 /* Number of 100 microseconds we wait for PCI Express master disable */
511 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
513 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
515 /* Number of milliseconds for NVM auto read done after MAC reset. */
528 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
587 /* NVM Addressing bits based on type (0-small, 1-large) */
635 /* length of string needed to store PBA number */
641 /* PBA (printed board assembly) number words */
647 /* NVM Commands - SPI */
651 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
679 /* PCI/PCI-X/PCI-EX Config space */
683 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
712 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
720 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
730 /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */
737 /* Number of times we will attempt to autonegotiate before downshifting if we
742 /* Number of times we will attempt to autonegotiate before downshifting if we
760 * 15-5: page
761 * 4-0: register offset
784 /* Page 193 - Port Control Registers */
790 /* Page 194 - KMRN Registers */