supported\-frequencies\-hz (full) in projects: linux

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched +full:supported +full:- +full:frequencies +full:- +full:hz (Results 1 – 11 of 11) sorted by relevance

/illumos-gate/usr/src/uts/sun4u/os/
H A D	mach_mp_startup.c	35 * Useful for disabling MP bring-up for an MP capable kernel 41 * Init CPU info - get CPU type info for processor_info system call. 46 processor_info_t pi = &cp->cpu_type_info; in init_cpu_info() 47 int cpuid = cp->cpu_id; in init_cpu_info() 50 cp->cpu_fpowner = NULL; / not used for V9 / in init_cpu_info() 53 Get clock-frequency property from cpunodes[] for the CPU. in init_cpu_info() 55 pi->pi_clock = (cpunode->clock_freq + 500000) / 1000000; in init_cpu_info() 58 * Current frequency in Hz. in init_cpu_info() 60 cp->cpu_curr_clock = cpunode->clock_freq; in init_cpu_info() 63 * Supported frequencies. in init_cpu_info() [all …]
/illumos-gate/usr/src/uts/sun4v/os/
H A D	mach_mp_startup.c	41 * Useful for disabling MP bring-up for an MP capable kernel 47 * Init CPU info - get CPU type info for processor_info system call. 52 processor_info_t pi = &cp->cpu_type_info; in init_cpu_info() 53 int cpuid = cp->cpu_id; in init_cpu_info() 56 cp->cpu_fpowner = NULL; / not used for V9 / in init_cpu_info() 59 Get clock-frequency property from cpunodes[] for the CPU. in init_cpu_info() 61 pi->pi_clock = (cpunode->clock_freq + 500000) / 1000000; in init_cpu_info() 64 * Current frequency in Hz. in init_cpu_info() 66 cp->cpu_curr_clock = cpunode->clock_freq; in init_cpu_info() 69 * Supported frequencies. in init_cpu_info() [all …]
/illumos-gate/usr/src/uts/common/io/sdcard/adapters/sdhost/
H A D	sdhost.c	200 ddi_get16(ss->ss_acch, (void )(ss->ss_regva + reg)) 202 ddi_put16(ss->ss_acch, (void )(ss->ss_regva + reg), val) 204 ddi_get32(ss->ss_acch, (void )(ss->ss_regva + reg)) 206 ddi_put32(ss->ss_acch, (void )(ss->ss_regva + reg), val) 208 ddi_get64(ss->ss_acch, (void )(ss->ss_regva + reg)) 211 ddi_get8(ss->ss_acch, (void )(ss->ss_regva + reg)) 213 ddi_put8(ss->ss_acch, (void )(ss->ss_regva + reg), val) 219 If ever anyone uses PIO on SPARC, we have to endian-swap. But we 304 shp->sh_slots[i].ss_num = -1; in sdhost_attach() 311 shp->sh_dmaattr.dma_attr_version = DMA_ATTR_V0; in sdhost_attach() [all …]
/illumos-gate/usr/src/uts/common/sys/
H A D	cpuvar.h	`79 * Per-CPU data. 88 processorid_t cpu_seqid; /* sequential CPU id (0..ncpus-1) / 103 - cpu_lock held 104 * - preemption disabled via kpreempt_disable 105 * - PIL >= DISP_LEVEL 106 * - acting thread is an interrupt thread 107 * - all other CPUs are paused 133 char cpu_runrun; /* scheduling flag - set to preempt / 159 cpu_stats_t cpu_stats; / per-CPU statistics / 182 struct nvlist cpu_props; /* pool-related properties */ [all …]`
/illumos-gate/usr/src/uts/i86pc/os/
H A D	mp_startup.c	95 * Useful for disabling MP bring-up on a MP capable system. 124 * Init CPU info - get CPU type info for processor_info system call. 129 processor_info_t pi = &cp->cpu_type_info; in init_cpu_info() 132 Get clock-frequency property for the CPU. in init_cpu_info() 134 pi->pi_clock = cpu_freq; in init_cpu_info() 137 * Current frequency in Hz. in init_cpu_info() 139 cp->cpu_curr_clock = cpu_freq_hz; in init_cpu_info() 142 * Supported frequencies. in init_cpu_info() 144 if (cp->cpu_supp_freqs == NULL) { in init_cpu_info() 148 (void) strcpy(pi->pi_processor_type, "i386"); in init_cpu_info() [all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A D	reg_addr.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 86 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 87 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 88 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 90 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 92 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 100 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_bb.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_k2.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_e5.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_ah_compile15.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 87 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 96 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 98 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 144 …_SYS_ERR (0x1<<30) // Fatal or Non-Fatal Error Message s… 148 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… 149 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… [all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D	57712_reg.h	3 …//ACCESS:RW DataWidth:0x2 Description: Defines the number of sets - 3 - 256 ;2- 128; 1- 64; 0- 32 9 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 10 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 11 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 12 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 13 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 14 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 15 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 16 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 17 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… [all …]