| /linux/arch/m68k/ifpsp060/ |
| H A D | os.S | 58 | or supervisor application space. The examples below use simple "move"
59 | instructions for supervisor mode applications and call _copyin()/_copyout()
76 | Writes to data memory while in supervisor mode.
79 | a0 - supervisor source address
82 | 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
89 btst #0x5,0x4(%a6) | check for supervisor state
107 | Reads from data/instruction memory while in supervisor mode.
111 | a1 - supervisor destination address
113 | 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
122 btst #0x5,0x4(%a6) | check for supervisor state
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| H A D | CHANGES | 91 bit 18:16 = x10 (TM; x = 1 for supervisor mode)
113 bit 18:16 = x01 (TM; x = 1 for supervisor mode)
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| H A D | iskeleton.S | 72 btst #0x5,%sp@ | supervisor bit set in saved SR?
192 | d0 = `xxxxxxff -> supervisor; `xxxxxx00 -> user
258 | d0 = `xxxxxxff -> supervisor; `xxxxxx00 -> user
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | riscv,cpu-intc.yaml | 16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
20 time timer that is controlled via Supervisor Binary Interface (SBI) calls
25 All RISC-V systems that conform to the supervisor ISA specification are
50 The interrupt sources are defined by the RISC-V supervisor ISA manual,
52 supervisor mode:
53 - Source 1 is the supervisor software interrupt, which can be sent by
55 - Source 5 is the supervisor timer interrupt, which can be configured
57 - Source 9 is the supervisor external interrupt, which chains to all
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| /linux/arch/m68k/fpsp040/ |
| H A D | skeleton.S | 377 btst #0x5,%sp@ | supervisor bit set in saved SR?
387 | mem_write --- write to user or supervisor address space
389 | Writes to memory while in supervisor mode. copyout accomplishes
393 | a0 - supervisor source address
397 | The supervisor source address is guaranteed to point into the supervisor
404 | If the EXC_SR shows that the exception was from supervisor space,
406 | there shouldn't be any supervisor mode floating point exceptions.
410 btstb #5,EXC_SR(%a6) |check for supervisor state
427 | mem_read --- read from user or supervisor address space
429 | Reads from memory while in supervisor mode. copyin accomplishes
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| H A D | x_store.S | 167 exg %a0,%a1 |a0=supervisor source, a1=user dest
231 exg %a0,%a1 |a0=supervisor source, a1=user dest
251 exg %a0,%a1 |a0=supervisor source, a1=user dest
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| /linux/Documentation/devicetree/bindings/riscv/ |
| H A D | extensions.yaml | 126 The standard Smaia supervisor-level extension for the advanced
151 The standard Ssaia supervisor-level extension for the advanced
152 interrupt architecture for supervisor-mode-visible csr and
158 The standard Sscofpmf supervisor-level extension for count overflow
170 The standard Sstc supervisor-level extension for time compare as
176 The standard Svade supervisor-level extension for SW-managed PTE A/D
184 unknown whether the platform uses Svade or Svadu. Supervisor
187 2) Only Svade present in DT => Supervisor must assume Svade to be
189 3) Only Svadu present in DT => Supervisor must assume Svadu to be
191 4) Both Svade and Svadu present in DT => Supervisor must assume
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| /linux/arch/microblaze/include/asm/ |
| H A D | mmu.h | 36 # define PP_RWXX 0 /* Supervisor read/write, User none */
37 # define PP_RWRX 1 /* Supervisor read/write, User read */
38 # define PP_RWRW 2 /* Supervisor read/write, User read/write */
39 # define PP_RXRX 3 /* Supervisor read, User read */
44 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
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| /linux/Documentation/hwmon/ |
| H A D | sl28cpld.rst | 21 supervisor. In the future there might be other flavours and additional
24 The fan supervisor has a 7 bit counter register and a counter period of 1
25 second. If the 7 bit counter overflows, the supervisor will automatically
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| H A D | pli1209bc.rst | 8 * Digital Supervisor PLI1209BC
22 The Vicor PLI1209BC is an isolated digital power system supervisor that provides
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| /linux/tools/arch/riscv/include/asm/ |
| H A D | csr.h | 12 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
14 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
16 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
18 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
301 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
305 /* Supervisor-Level Interrupts (AIA) */
309 /* Supervisor-Level High-Half CSRs (AIA) */
396 /* Virtual Interrupts for Supervisor Level (AIA) */
466 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
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| /linux/arch/riscv/include/asm/ |
| H A D | csr.h | 13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
333 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
337 /* Supervisor-Level Interrupts (AIA) */
341 /* Supervisor-Level High-Half CSRs (AIA) */
430 /* Virtual Interrupts for Supervisor Level (AIA) */
511 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
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| /linux/arch/powerpc/include/asm/book3s/32/ |
| H A D | mmu-hash.h | 57 #define PP_RWXX 0 /* Supervisor read/write, User none */
58 #define PP_RWRX 1 /* Supervisor read/write, User read */
59 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
60 #define PP_RXRX 3 /* Supervisor read, User read */
65 #define SR_KS 0x40000000 /* Supervisor key */
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| /linux/Documentation/arch/x86/x86_64/ |
| H A D | fred.rst | 20 establishes the full supervisor context and that event return
53 Full supervisor/user context
56 FRED event delivery atomically save and restore full supervisor/user
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| /linux/arch/m68k/include/asm/ |
| H A D | mcfdma.h | 89 #define MCFDMA_DMR_DSTT_SD 0x00001400L /* Destination is supervisor data */
90 #define MCFDMA_DMR_DSTT_SC 0x00001800L /* Destination is supervisor code */
101 #define MCFDMA_DMR_SRCT_SD 0x00000014L /* Source is supervisor data */
102 #define MCFDMA_DMR_SRCT_SC 0x00000018L /* Source is supervisor code */
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| H A D | m54xxacr.h | 36 #define ACR_SUPER 0x00002000 /* Supervisor mode only */
43 #define ACR_SP 0x00000008 /* Supervisor protect */
96 * cacheable and supervisor access only.
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| H A D | mcfmmu.h | 60 #define MMUSR_SPF 0x00000020 /* Supervisor protect fault */
79 #define MMUDR_SP 0x00000020 /* Supervisor access enable */
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| /linux/arch/sparc/include/asm/ |
| H A D | pcr.h | 20 #define PCR_STRACE 0x00000002 /* Trace supervisor events */
39 #define PCR_N4_STRACE 0x00000008 /* Trace supervisor events */
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| H A D | pgtsrmmu.h | 38 * for both supervisor and user pages.
42 * characteristics of supervisor ptes
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| H A D | iommu_32.h | 63 #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
77 #define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
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| /linux/drivers/reset/ |
| H A D | reset-tps380x.c | 3 * TI TPS380x Supply Voltage Supervisor and Reset Controller Driver
125 MODULE_DESCRIPTION("TI TPS380x Supply Voltage Supervisor and Reset Driver");
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| /linux/Documentation/translations/zh_CN/core-api/ |
| H A D | errseq.rst | 77 struct supervisor {
82 struct supervisor su;
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| /linux/drivers/hwmon/pmbus/ |
| H A D | pli1209bc.c | 3 * Hardware monitoring driver for Vicor PLI1209BC Digital Supervisor
97 * The pli1209 digital supervisor only contains a single BCM, making
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| /linux/Documentation/arch/riscv/ |
| H A D | uabi.rst | 29 #. Standard supervisor-level extensions (starting with 'S') will be listed
30 after standard unprivileged extensions. If multiple supervisor-level
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| /linux/arch/openrisc/include/asm/ |
| H A D | spr_defs.h | 215 #define SPR_SR_SM 0x00000001 /* Supervisor Mode */
231 #define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
275 #define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
276 #define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
517 #define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */
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