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/linux/Documentation/devicetree/bindings/pwm/
H A Dallwinner,sun4i-a10-pwm.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/allwinner,sun4i-a10-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 PWM
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#pwm-cells":
19 - const: allwinner,sun4i-a10-pwm
20 - const: allwinner,sun5i-a10s-pwm
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/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h6.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/sun50i-h6-ccu.h>
6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-tcon-top.h>
10 #include <dt-bindings/reset/sun50i-h6-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h>
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/linux/drivers/clk/sunxi-ng/
H A Dccu-sun50i-h6-r.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
19 #include "ccu-sun50i-h6-r.h"
27 "iosc", "pll-periph0" };
53 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
55 static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
71 .hw.init = CLK_HW_INIT_PARENTS("r-apb2",
82 * "Allwinner H6 V200 User Manual V1.1"; and the parent APB buses are verified
85 static SUNXI_CCU_GATE(r_apb1_timer_clk, "r-apb1-timer", "r-apb1",
87 static SUNXI_CCU_GATE(r_apb1_twd_clk, "r-apb1-twd", "r-apb1",
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H A Dccu-sun50i-h6.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
23 #include "ccu-sun50i-h6.h"
42 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
58 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
75 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
92 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
107 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
129 .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
147 .hw.init = CLK_HW_INIT("pll-video1", "osc24M",
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H A Dccu-sun50i-h616.c1 // SPDX-License-Identifier: GPL-2.0
4 * Based on the H6 CCU driver, which is:
8 #include <linux/clk-provider.h>
25 #include "ccu-sun50i-h616.h"
44 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
60 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
75 .hw.init = CLK_HW_INIT("pll-ddr1", "osc24M",
92 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
109 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
124 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
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/linux/drivers/pwm/
H A Dpwm-sun4i.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 * - When outputing the source clock directly, the PWM logic will be bypassed
21 #include <linux/pwm.h>
47 #define PWM_PRD(prd) (((prd) - 1) << 16)
100 return readl(sun4ichip->base + offset); in sun4i_pwm_readl()
106 writel(val, sun4ichip->base + offset); in sun4i_pwm_writel()
110 struct pwm_device *pwm, in sun4i_pwm_get_state() argument
118 clk_rate = clk_get_rate(sun4ichip->clk); in sun4i_pwm_get_state()
120 return -EINVAL; in sun4i_pwm_get_state()
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/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-sun50i-h6.c1 // SPDX-License-Identifier: GPL-2.0
3 * Allwinner H6 SoC pinctrl driver.
13 #include "pinctrl-sunxi.h"
346 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
603 { .compatible = "allwinner,sun50i-h6-pinctrl", },
610 .name = "sun50i-h6-pinctrl",
/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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