Searched +full:sun4i +full:- +full:a10 +full:- +full:axi +full:- +full:clk (Results 1 – 7 of 7) sorted by relevance
| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | allwinner,sun4i-a10-gates-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Bus Gates Clock
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
24 - const: allwinner,sun4i-a10-gates-clk
25 - const: allwinner,sun4i-a10-axi-gates-clk
[all …]
|
| H A D | allwinner,sun4i-a10-axi-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-axi-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 AXI Clock
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
21 - allwinner,sun4i-a10-axi-clk
22 - allwinner,sun8i-a23-axi-clk
[all …]
|
| H A D | allwinner,sun4i-a10-ahb-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 AHB Clock
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
21 - allwinner,sun4i-a10-ahb-clk
22 - allwinner,sun6i-a31-ahb1-clk
[all …]
|
| /linux/drivers/clk/sunxi/ |
| H A D | clk-simple-gates.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
41 number = of_property_count_u32_elems(node, "clock-indices"); in sunxi_simple_gates_setup()
42 of_property_read_u32_index(node, "clock-indices", number - 1, &number); in sunxi_simple_gates_setup()
44 clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL); in sunxi_simple_gates_setup()
45 if (!clk_data->clks) in sunxi_simple_gates_setup()
48 of_property_for_each_u32(node, "clock-indices", index) { in sunxi_simple_gates_setup()
49 of_property_read_string_index(node, "clock-output-names", in sunxi_simple_gates_setup()
[all …]
|
| H A D | clk-sunxi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
45 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
[all …]
|
| /linux/drivers/clk/sunxi-ng/ |
| H A D | ccu-sun4i-a10.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
28 #include "ccu-sun4i-a10.h"
38 .hw.init = CLK_HW_INIT("pll-core",
50 * With sigma-delta modulation for fractional-N on the audio PLL,
73 .hw.init = CLK_HW_INIT("pll-audio-base",
91 .hw.init = CLK_HW_INIT("pll-video0",
106 .hw.init = CLK_HW_INIT("pll-ve",
119 .hw.init = CLK_HW_INIT("pll-ve",
132 .hw.init = CLK_HW_INIT("pll-ddr-base",
[all …]
|
| /linux/ |
| H A D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
[all …]
|