Searched +full:stm32mp25 +full:- +full:pcie +full:- +full:ep (Results 1 – 5 of 5) sorted by relevance
| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | st,stm32-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/st,stm32-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32MP25 PCIe Endpoint
10 - Christian Bruel <christian.bruel@foss.st.com>
13 PCIe endpoint controller based on the Synopsys DesignWare PCIe core.
16 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
17 - $ref: /schemas/pci/st,stm32-pcie-common.yaml#
21 const: st,stm32mp25-pcie-ep
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| H A D | st,stm32-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/st,stm32-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STM32MP25 PCIe RC/EP controller
10 - Christian Bruel <christian.bruel@foss.st.com>
13 STM32MP25 PCIe RC/EP common properties
18 description: PCIe system clock
23 power-domains:
26 access-controllers:
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| /linux/drivers/pci/controller/dwc/ |
| H A D | pcie-stm32-ep.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * STMicroelectronics STM32MP25 PCIe endpoint driver.
18 #include "pcie-designware.h"
19 #include "pcie-stm32.h"
31 static void stm32_pcie_ep_init(struct dw_pcie_ep *ep) in stm32_pcie_ep_init() argument
33 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in stm32_pcie_ep_init()
44 regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, in stm32_pcie_enable_link()
55 regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, STM32MP25_PCIECR_LTSSM_EN, 0); in stm32_pcie_disable_link()
63 dev_dbg(pci->dev, "Enable link\n"); in stm32_pcie_start_link()
67 dev_err(pci->dev, "PCIe cannot establish link: %d\n", ret); in stm32_pcie_start_link()
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
10 bool "DesignWare PCIe debugfs entries"
14 Say Y here to enable debugfs entries for the PCIe controller. These
30 bool "Amazon Annapurna Labs PCIe controller"
36 Say Y here to enable support of the Amazon's Annapurna Labs PCIe
37 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
39 required only for DT-based platforms. ACPI platforms with the
40 Annapurna Labs PCIe controller don't need to enable this.
43 bool "AMD MDB Versal2 PCIe controller"
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| /linux/ |
| H A D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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