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Searched +full:stm32 +full:- +full:dsi (Results 1 – 13 of 13) sorted by relevance

/linux/Documentation/devicetree/bindings/display/
H A Dst,stm32-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DSI host controller
10 - Philippe Cornu <philippe.cornu@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
17 - $ref: dsi-controller.yaml#
21 const: st,stm32-dsi
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H A Dst,stm32-ltdc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-ltdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 lcd-tft display controller
10 - Philippe Cornu <philippe.cornu@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
15 const: st,stm32-ltdc
22 - description: events interrupt line.
23 - description: errors interrupt line.
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/linux/arch/arm/boot/dts/st/
H A Dstm32f469.dtsi1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */
8 dsi: dsi@40016c00 { label
9 compatible = "st,stm32-dsi";
11 resets = <&rcc STM32F4_APB2_RESET(DSI)>;
12 reset-names = "apb";
14 clock-names = "pclk", "ref";
H A Dstm32mp157.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
16 clock-names = "bus" ,"core";
20 dsi: dsi@5a000000 { label
21 compatible = "st,stm32-dsi";
23 clocks = <&rcc DSI>, <&clk_hse>, <&rcc DSI_PX>;
24 clock-names = "pclk", "ref", "px_clk";
25 phy-dsi-supply = <&reg18>;
27 reset-names = "apb";
31 #address-cells = <1>;
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H A Dstm32f769.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 compatible = "st,stm32f4-bxcan";
14 interrupt-names = "tx", "rx0", "rx1", "sce";
22 compatible = "st,stm32f4-gcan", "syscon";
27 dsi: dsi@40016c00 { label
28 compatible = "st,stm32-dsi";
31 clock-names = "pclk", "ref";
32 resets = <&rcc STM32F7_APB2_RESET(DSI)>;
33 reset-names = "apb";
H A Dstm32f769-disco.dts2 * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
45 #include "stm32f769-pinctrl.dtsi"
46 #include <dt-bindings/input/input.h>
47 #include <dt-bindings/gpio/gpio.h>
50 model = "STMicroelectronics STM32F769-DISCO board";
51 compatible = "st,stm32f769-disco", "st,stm32f769";
55 stdout-path = "serial0:115200n8";
63 reserved-memory {
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H A Dstm32f469-disco.dts2 * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 /dts-v1/;
50 #include "stm32f469-pinctrl.dtsi"
51 #include <dt-bindings/gpio/gpio.h>
52 #include <dt-bindings/input/input.h>
55 model = "STMicroelectronics STM32F469i-DISCO board";
56 compatible = "st,stm32f469i-disco", "st,stm32f469";
60 stdout-path = "serial0:115200n8";
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/linux/drivers/gpu/drm/stm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 Enable support for the on-chip display controller on
15 STMicroelectronics STM32 MCUs.
17 will be called stm-drm.
20 tristate "STMicroelectronics specific extensions for Synopsys MIPI DSI"
24 Choose this option for MIPI DSI support on STMicroelectronics SoC.
H A Ddw_mipi_dsi-stm.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
28 /* DSI digital registers & bit definitions */
32 /* DSI wrapper registers & bit definitions */
35 #define WCFGR_DSIM BIT(0) /* DSI Mode */
39 #define WCR_DSIEN BIT(3) /* DSI ENable */
63 /* dsi color format coding according to the datasheet */
86 struct dw_mipi_dsi *dsi; member
94 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val) in dsi_write() argument
96 writel(val, dsi->base + reg); in dsi_write()
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/linux/Documentation/arch/arm/stm32/
H A Dstm32f769-overview.rst6 ------------
8 The STM32F769 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @216MHz
12 - 2MB internal flash, 512KBytes internal RAM (+4KB of backup SRAM)
13 - FMC controller to connect SDRAM, NOR and NAND memories
14 - Dual mode QSPI
15 - SD/MMC/SDIO support*2
16 - Ethernet controller
17 - USB OTFG FS & HS controllers
18 - I2C*4, SPI*6, CAN*3 busses support
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/linux/drivers/clk/stm32/
H A Dclk-stm32mp1.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
9 #include <linux/clk-provider.h>
17 #include <linux/reset-controller.h>
21 #include <dt-bindings/clock/stm32mp1-clks.h>
23 #include "reset-stm32.h"
171 "ck_hse", "pll4_r", "clk-hse-div2"
384 /* STM32 Composite clock */
397 struct gate_cfg *gate_cfg = cfg->cfg; in _clk_hw_register_gate()
400 cfg->name, in _clk_hw_register_gate()
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H A Dclk-stm32mp25.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
8 #include <linux/clk-provider.h>
12 #include "clk-stm32-core.h"
13 #include "reset-stm32.h"
16 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
17 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
20 #define SECF_NONE -1
523 /* CSI-HOST */
539 /* CSI-PHY */
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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